Cadence further defines and extends its SoC realization strategy

Microelectronics International

ISSN: 1356-5362

Article publication date: 2 August 2011



(2011), "Cadence further defines and extends its SoC realization strategy", Microelectronics International, Vol. 28 No. 3.



Emerald Group Publishing Limited

Copyright © 2011, Emerald Group Publishing Limited

Cadence further defines and extends its SoC realization strategy

Article Type: New products From: Microelectronics International, Volume 28, Issue 3

Cadence have further detailed its SoC Realization strategy, a key tenet of the EDA360 vision outlined last year. SoCs require integrating IP solutions from three primary categories: memory and storage, interface, and compute.

Given the significant impact that memory controller IP has on the overall performance of the SoC and system, Cadence is expanding the in-house development of comprehensive memory and storage controller IP to ensure maximum robustness and performance. The company plans to continue Denali’s tradition of developing high-quality IP in parallel with industry standards, giving customers the ability to be first-to-market with differentiated SoC solutions. The company also plans to support its IP with a comprehensive integration environment that is unparalleled in the industry.

For interface IP, Cadence will offer high-performance interface solutions, such as PCI Express Gen2 and Gen3, as well as Gibabit Ethernet (GbE), 10 and 40 GbE solutions. The combined Denali and Cadence services team offers decades of design expertise, and will continue to deliver highly optimized, integrated IP solutions.

In the compute category, Cadence will continue to collaborate with leading IP providers to ensure it can support the compute needs of SoC designers. The group’s primary focus will be on ensuring successful integration through advanced methodologies, tools and reference flows that take a holistic approach to SoC design and verification.


DDR4 controller IP, verification IP and memory models are available now, and supported by both Cadence and third-party design tools and methodologies. A soft DDR4 PHY is expected to be available this quarter, while a hard PHY solution for 28-nm TSMC geometries is expected to be available by Q3 2011. For more information, please visit web site:

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