Citation
(2010), "Synopsys launches DesignWare HDMI 1.4 Tx/Rx controller and PHY IP solutions for 40 nm process technologies", Microelectronics International, Vol. 27 No. 2. https://doi.org/10.1108/mi.2010.21827bad.009
Publisher
:Emerald Group Publishing Limited
Copyright © 2010, Emerald Group Publishing Limited
Synopsys launches DesignWare HDMI 1.4 Tx/Rx controller and PHY IP solutions for 40 nm process technologies
Article Type: New products From: Microelectronics International, Volume 27, Issue 2
Synopsys, Inc. have announced the availability of high-quality DesignWare® HDMI™ 1.4 transmitter (Tx) and receiver (Rx) digital controllers and PHY IP solutions that are compliant to the standard specification. With full support for new features of the HDMI 1.4 specification including HEAC, 3D formats, real-time content signalling, 4,000×2,000 resolution and 10.2 Gbps aggregate bandwidth, the DesignWare HDMI IP enables designers to quickly incorporate differentiated functionality into their digital TV and home theatre applications with less risk and improved time-to-market.
With designers incorporating networking capabilities in next generation home entertainment devices, the HEAC block in the DesignWare HDMI 1.4 solution helps simplify the connectivity between internet-enabled digital home devices by enabling the transfer of Ethernet and audio frames through a single HDMI cable. The DesignWare IP for HDMI 1.4 also incorporates all 3D formats, which allows device manufacturers to heighten the viewing experience by supporting 3D techniques such as full side-by-side, half side-by-side, and frame alternative. The real-time content signalling capability enables televisions to automatically optimise the picture setting with no user intervention. Support for 4,000×2,000 resolution delivers up to four times the resolution of 1080 p, providing the same resolution as state-of-the-art digital cinema systems.
The DesignWare HDMI IP solution includes a comprehensive set of IP deliverables including baseline software drivers for system development, which help designers quickly embed this complex interface into next generation multimedia system-on-chips (SoCs). Furthermore, the solution provides the following:
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Compliance with HDMI and HDCP specifications with certification from the NXP HDMI authorised testing centre and successful interoperability results from HDCP plugfest events.
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A superior analogue front end that supports up to 20 ft category two-certified HDMI cables, while maintaining high performance.
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Digital controllers delivered in configurable RTL allow designers to optimise gate count and power consumption by choosing only the features required in their application.
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PHY offering low power consumption and small die area.
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Numerous optional features such as HDCP encryption engine, audio formats, audio DMA engine, and system-bus interfaces which help ease the integration effort.
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System validation based on the Synopsys Confirma™ HAPS-51 rapid prototyping platform.
For further information, please visit the web site: www.synopsys.com