TSMC first to deliver 40 nm process technology

Microelectronics International

ISSN: 1356-5362

Article publication date: 25 July 2008



(2008), "TSMC first to deliver 40 nm process technology", Microelectronics International, Vol. 25 No. 3. https://doi.org/10.1108/mi.2008.21825cad.008



Emerald Group Publishing Limited

Copyright © 2008, Emerald Group Publishing Limited

TSMC first to deliver 40 nm process technology

Article Type: New products From: Microelectronics International, Volume 25, Issue 3

Taiwan Semiconductor Manufacturing Company, Ltd have unveiled the foundry’s first 40 nm manufacturing process technology.

The new node supports a performance-driven general purpose (40G) technology and a power-efficient low-power (40LP) technology. It features a full design service package and a design ecosystem that covers verified third party IP, third party EDA tools, TSMC-generated SPICE models and foundation IPs. First wafers out are expected in the second quarter of 2008.


  • a 2.35 times raw gate density improvement over 65 nm;

  • active power down-scaling of up to 15 per cent over 45 nm;

  • smallest SRAM cell size and macro size in the industry;

  • general purpose and low-power versions for broad product applications;

  • dozens of customers in the design pipeline today; and

  • frequent and regular CyberShuttleTM, MPW prototyping running.

Following successful tapeouts and customer announcements of its 45 nm process technology in 2007, TSMC has moved forward quickly and developed an enhanced 40LP and 40G process that delivers industry-leading performance with 40 nm density. The 45 nm node provided double the gate density of 65 nm, while the new 40 nm node features manufacturing innovations that enable its LP and G processes to deliver a 2.35 raw gate density improvement of the 65 nm offering. The transition from 45 to 40 nm low-power technology reduces power scaling up to 15 per cent.

“Our design flow can take designs started at 45 nm and target it toward the advantages of 40 nm”, said John Wei, Senior Director of Advanced Technology Marketing at TSMC. “A lot of TSMC development work has gone into ensuring that this transition is truly transparent. Designers need only concentrate on achieving their performance objectives”, he said.

TSMC has developed the 40LP for leakage-sensitive applications such as wireless and portable devices and its 40G variant targeting performance applications including CPU, graphic processing unit, game console, networking and FPGA designs and other high-performance consumer devices. The 40 nm footprint is linearly shrunk and the SRAM performance is fully maintained when compared to its 45 nm counterpart, its SRAM cell size is now the smallest in the industry at 0.242 μm2.

A full range of mixed signal and RF options accompany the 40G and 40LP processes along with embedded DRAM, to match the breath of applications that can take advantage of the new node’s unbeatable size and performance combination.

The 40 nm process employs a combination of 193 nm immersion photolithography and extreme low-k material. The logic family includes a low-power triple-gate oxide option to support high-performance wireless and portable applications. Both, the G and the LP processes offer multiple Vt core devices and 1.8, 2.5 V I/O options to meet different product requirements.

TSMC’s CyberShuttle prototyping service can be booked for 40 nm designs in June, August, October and December this year and first wave 45/40 nm customers have already used above 200 blocks on completed multi-project wafer runs. The 40G and LP processes will initially run in TSMCs 12 in. wafer Fab 12 and will be transferred to Fab 14 as demand ramps.

For further information, please visit the web site: www.tsmc.com

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