Synopsys and TSMC collaborate on advanced HSPICE modelling technology for 40 nm processes

Microelectronics International

ISSN: 1356-5362

Article publication date: 25 July 2008

Citation

(2008), "Synopsys and TSMC collaborate on advanced HSPICE modelling technology for 40 nm processes", Microelectronics International, Vol. 25 No. 3. https://doi.org/10.1108/mi.2008.21825cad.005

Publisher

:

Emerald Group Publishing Limited

Copyright © 2008, Emerald Group Publishing Limited


Synopsys and TSMC collaborate on advanced HSPICE modelling technology for 40 nm processes

Article Type: New products From: Microelectronics International, Volume 25, Issue 3

Snopsys, Inc. have released news of the TSMC modelling interface (TMI) methodology, which has been developed from Synopsys’ production proven protocol for integrating custom device models into HSPICE(R), HSIM(TM) and NanoSim(R) transistor-level circuit simulators. The TMI methodology delivers an innovative and efficient device modelling approach for TSMC’s process technologies at 40 nm and below. This new methodology, on average, improves simulation time and reduces memory usage by 5X.

With device geometries shrinking at every new process node, MOSFET model complexity has increased in order to accurately represent the impact of new physical effects. At 40 nm, the industry-standard BSIM-4 MOSFET model must now take into consideration mechanical stress effects in silicon, and layout dependencies that alter the characteristics of individual device instances based on their placement and proximity to other devices. Standardisation of stress-effect modelling is extremely difficult because of the differences that exist in each application of strain engineering, and requires customisation of models for every process.

For further information, please visit the web site: www.synopsys.com