Emerald Group Publishing Limited
Copyright © 2008, Emerald Group Publishing Limited
MicroTech 2008 Beaumont House, Old Windsor June 10 and 11 2008
Article Type: Exhibitions and conferences From: Microelectronics International, Volume 25, Issue 3
Beaumont House on Old Windsor can be traced back to 1300, but major rebuilding was undertaken in 1680. It was owned by the Duchess of Kent in 1741, later by Warren Hastings, the first Governor-General of India, and in 1861 it saw the foundation of Beaumont College, a boy’s boarding school which remained until 1967. After a period in the hands of ICL, it is now an extremely large conference centre (Figure 1).
Figure 1 Beaumont House on Old Windsor, location for MicroTech 2008
After a warm welcome from iMAPS UK, Chairman Andy Longford, all the various exhibitors introduced themselves to the delegates, whilst the room filled up. Like so many conferences, these days attendance on the first day was hardly punctual thanks mostly to the creaking infrastructure of the UK.
Steve Adamson from Asymtek talked about the first 40 years of Microlectronics Packaging from the standpoint of President of iMAPS, the USA. He looked at the microelectronics package revolution, constantly evolving. iMAPS provides means of communicating, educating and interacting at all levels; there are 22 iMAPS chapters in the USA, there are international chapters in 19 countries, and there are in excess of 10,000 members worldwide. No less than 293 companies are corporate members and Mr Adamson looked at how the iMAPS society had grown from the beginnings back in 1967, when it was known as the International Society of Hybrid Microelectronics.
It was thick film that brought people together in the first place; ceramic dual-in-line packages arrived in 1965, followed, between 1972 and 1978, by the microprocessor, and it was low-cost automation which allowed for components to be placed on both sides of the PCB. In 1982, the move to surface mount, with ceramic pin grid arrays and ceramic chip carriers leading on to pin grid arrays, and then to microprocessors in PGA packages. Now, the predicted need for embedded components was explained, with greater functionality, reduced size, etc. Mr Spock in Star Trek had a “mobile phone” back in 1966, and they now have embedded components, in fact Motorola were using them back in 1989. A 3D device packaging, with package stacking, die stacking and wafer stacking, is to be with us in the coming years, and Moore’s law continues on. Chip scale packaging, embedded dies and the passive life cycles of chip components were also discussed. As for the future, iMAPS initiatives included lab on a chip; solar panels; LED packaging; nano-materials and direct methanol fuel cell technology. Interestingly, there are implications for the need to pursue low-cost labour for manufacture, and high-tech countries might just have high-tech production as well, as the passives and actives become embedded and the PCB shop and the assembler merge as one.
Dr Zaid Aboush from CSR in Cambridge talked about optimising power supply connections in BGA packages. Power supplies have limited current capacity, so having no decoupling capacitor is ideal. The supply decoupling capacitor is basically a high-pass filter which is open at DC and short circuit at higher frequencies. In practice, multiple capacitors might be needed to provide a short circuit for all harmonics as well as the baseband for the analogue. Placing the supply de-coupling capacitor next to the chip is ideal, but may prove impractical. Optimised decoupling was investigated using a VDD/VSS PCB-package model with 1 μF capacitors attached, and it was demonstrated that chip impedance has to be considered in the design stage, and a compromise has to be struck between low-loss and low-noise design. There was no difference between analogue and digital worlds here.
Thick film sensors/actuators for LTCC-based MEMS were evaluated by Marko Hrovat from the Wroclaw University of Technology. For low-temperature sintering of ceramic – MEMS there has to be a glass face, and Marko and his team had evaluated three different LTCC tape materials, conventional, lead-free and lead-free zero shrinkage, namely Du Pont 951, ESL 41020, and Heraeus HL-2000. The microstructures on all three showed varied characteristics, They studied compatibility and material composition, and they looked at the possible interactions between thick film layers and LTCC substrates, using X-ray defraction analysis. Testing was exhaustive, and the results were explained. In the final analysis, the results of PZT film on LTCC looked good.
Dr Karl Heinz Bock is the Deputy Director of The Fraunhofer Institut. His subject was the integration of peripheries with electronics in foils, produced on a reel-to-reel (R2R) basis. Here, polymer electronics are created using copper foil, a screen-printed PI or solder resists with via technology and then screen printed metallisation. Minimal lines and spaces on copper are 15 μm, and lines and spaces of the second layer are 200 um. Copy chart here if possible. They can integrate very thin chips, 10 μm thick, perfect for RFID, where the R2R assembly of thin chip with an FC bond by use of ACA is one end use. Such foil-based electronics can be applied to products such as temperature sensors, capacitive chemical sensors, and electrochemical electrodes. In the field of diagnostic systems, the development of smart plastic was described, where a solar cell, a battery, an integrated EL lamp and electronics for power management were integrated on a foil substrate and used, for example, for point of care diagnosis. R2R base manufacturing technology for electronic systems integration led to a wide range of applications, such as the. Microfluid cartridge, electro luminescence OLEDS, medical wrist watch straps to monitor humidity and temperature. Integrated systems in foil could be used as a. network system on the body. Large area multi-functional systems can be used for displays, can be integrated in clothes and textiles, solar energy scavenging, as diagnostics, in bandages as implantables, and at the low-cost end – disposables such as RFID.
After lunch MicroTech 2008 ran a Market Watch Session, introduced by Andy Longford. Here, five distinguished guests each spoke for awhile and then formed a panel for a discussion. Aubrey Dunford of AFDEC opened for the team who addressed the question – UK Electronics – where has it gone? First of all, he pondered, what do you mean by UK Electronics – the design, the manufacture, or the control? What has gone, and was it part of what we do anyway? Distribution market for his sector, components, was looking flat, but overall there is a very gentle and consistent trend towards growth over the last 25 years. He cited examples, such as the digital communications bump where system X moved the UK telephone system into digital, and thus the start of the home PC and the home-based office. In his sector, the UK is a € 5 billion market for components, and component assemblies, and it is rising..
Nigel Rix of Electronics Knowledge Transfer Network (EKTN) explained how his organisation was created to look after the SME’s in the electronics market. EKTN uses highly efficient networking to communicate, and look at the knowledge pool, and this gives SME’s access to useful information, with opportunities such as the 2012 Olympic Games. Electronics in the UK still exists, but the big companies have mostly all gone. Now, it consists of small SMEs who are innovative in their own right, but they need a bit of help and happily there is EKTN.
Derek Boyd, of NMI, is the Chairman of the UK Electronics Alliance. He talked about the globalisation of innovation systems, which are science based but need support not least to improve the speed of innovation. What are we good at? Engineering skills, basic science and inventiveness, but not always so good at putting them into practice. He felt that electronics design should be a national competence, and here we do need to address some key weaknesses. Investment runs at £300 million a year, but we need a better return on the commercial take up. Regionalisation is a disaster for the UK, where funding goes to regions, often under political guidance, and electronics does not conform to neat pockets. But, the electronics industry in the UK is still here, it is innovative, but it needs tidying up and a bit of parental support from HMG.
Richard Wyatt runs The National Skills Academy for manufacturing. There are 11,000 electronics work places, of which 93 per cent are full. Electronics is a £3 billion market in the UK. The government recruited a retired Rear-Admiral, Rodney Leach, to report back on the nation’s skills shortages, and he came up with no less than 94 recommendations on skills requirements. We fall backwards in too many areas, he said. We should have 95 per cent adult literacy and numeracy, we have 69 per cent. We should have a 93 per cent GCSE pass rate with 40 per cent at level 4, but we only have 29 per cent. The UK is sliding down the league tables, and the “one size fits all” dogma on education in this country serves us ill. We need to use modern methods of education and beef it all up. His academy enables training which makes more money for the company involved. The academy is employer-led and is committed to raising the bar on training standards, raising them. It is all about competitiveness. Electronics in the UK? No, it is not gone, but the question is – where shall we take it?
Chris Bailey asked if the universities were doing enough. It was a fact that not enough engineers were coming out of universities. Peter Barnwell thought that the problem goes right down to the schools, and Russell Shipton agreed, we need to trigger the interest in the younger people before a career path in retail or social sciences enticed them away. Universities need to make electronic engineering sexy, and Derek Boyd thought that there should be an industry/government led initiative into schools to talk to pupils at an early stage in their education.
Chris Hunt of the NPL spoke on measuring true stress and strain for total energy density predictions of fatigue damage, using isothermal (−55/+125°C cycle) fatigue/stress. It is the CTE mismatch in the package that causes solder joints to fail. They used SAC 305 solder for the tests, and 2 mm cuts were made to the joint, and they applied mechanical wave form displacement to replicate the failure, measuring resistance on the cycle at the same time. Crack length helps predict failure, and they will continue their work using other alloys and materials. A 60°C saw more damage accumulated, but constant strain was not seen at that temperature. Cracks in the solder were seen but not in the joint, and crack lengths could be estimated with resistance measurements.
Bob Page knows all about reliability. His company specialises in the subject, and told us about tools which can be used to give us more data on reliability. It applies to electronic devices, circuit assemblies, and systems in their entirety. Factors that stack up and contribute to unreliability are time pressure, technical problems, poor project management complacency and responsibility (lack of). Chart of factors affecting lead-fee reliability. Methodology for reliability prediction included the highly accelerated life test which uses controlled environmental stresses applied to one or more pre-production samples to precipitate latent defects and to indicate areas requiring increased robustness. The sooner you can catch a problem the more money you will save. The cost of unreliability, per hour, is worth noting. It is £2.8 million in energy costs, £1.6 million in financial costs, and in manufacturing unreliability costs £1.4 million per hour.
Stress and strain was the theme of Chris Bailey’s paper on power modules failing. He looked at the physics of failure-based reliability. Common problem of all the components in a power module is the CTE mismatch, and that is a fact of life. He gave two good examples, a mass transit commuter train via high-speed inter-city train where, because the commuter train stops and starts more often there are more frequent temperature cycles, and the component failure rate is higher with the more frequent stopping train. A lot can go wrong in manufacturing. Prognostics – we are mimicking field conditions, but if we could have methods that could analyse data from the field trial then we would be happier.
Andy Longford gave the first paper on “Micro/nano systems – the future R&D and new challenges for Europe”. He brought the matter of the European Union’s next Framework Programme FP7 to the attention of the delegates, this runs from 2007 to 2013, and within this i2010 focuses on the EU’s R&D instruments and sets priorities for cooperation with the private sector to promote innovation and technological leadership. Two initiatives of interest here, ENIAC, and ARTEMIS. The budget for the latter is € 2.7 billion over seven years, 60 per cent of that budget is from industry.
Micro/nano systems are described as miniaturised systems able to sense, diagnose, describe and qualify a given situation; suggest or implement appropriate actions and interact with the user the environment or other smart systems. The main challenges here are many, and diverse. Illustrated were healthy aims – where intelligent sensors can be used within the human body to monitor or detect. Good food – brought the lab to the foodstuff from the land to the market. Sensation – monitoring brain activity, the body area network. MEMS and NEMS were described in detail.
Peter Barnwell had done a study of the performance of thermal vias within LTCC. One of the criticisms of LTCC is thermal conductivity, to which the answer is a thermal via. Du Pont 951 is an industry standard, but how do you design thermal vias? Peter explained how they had approached the test procedure, and the spacing of the vias, the closer they are together the better the conductivity. But what happens if you change the diameters? Small vias, such as 6mil, closely spaced, gives best performance. In total, 943 fits insertion loss simulation better than 9,512, and 943 gives better lower loss – 1 dB against 1.5 dB. Better as a product, but at a cost.
John Carr is from Heriot-Watt University, where he works for Renishaw on optical encoders. He illustrated a traditional optical encoder configuration, and explained that the problems encountered are the alignment requirements between the optical gratings and critically between the gratings and the photo detector array. At Heriot-Watt, they have proposed a novel solution utilising microsystems manufacturing techniques to monolithically integrate the traditional optical encoder read head components onto a single compound semiconductor chip. Demonstrated against a 4 μm pitch, this concept has been verified, achieving significantly relaxed alignment tolerances, AC:DC ratios of the order of 7:1 and SNR greater than 50:1 with dedicated electronics which achieve 2 MHz operation and therefore 4 m/s traverse speeds over 4 μm pitch scale.
“Durable high temperature electronics packaging for down well applications” was the title of a paper given by Steve Riches of GE Aviation Systems. High temperatures here means up to 250°C, and the electronics package has to last for 2,000 h with vibration, high pressure and in a potentially corrosive environment. This step change in temperature requirements changes the electronic packaging options, and the application is now more up in the sky rather than just down a well. Temperature changes can vary from −40 up to 250°C. Substrates inc high temperature PCBs, but perhaps not up to 250, and lead-free soldering will hardly withstand high temperatures such as these, so they are considering the use of ceramics, with various die attach systems, also lead-frames attached to chips on both sides, high-temperature solders, a whole raft of options, but in the end it will be the physics of failure approach that will probably provide the answers. Soldering may be one of the biggest problems to overcome, as is electro-migration, especially silver.
Figure 2 Dr Christian Val (left) of 3D Plus
Andrew Holland chaired the next session in which Dr Christian Val (Figure 2) of 3D Plus spoke on the subject of interconnection in 3D for SiP stacking of known good rebuilt wafers. The 3D Plus is a spin-off from Thales, and work for NASA, ESA, and are a small but highly profitable company. They manufacture memory, and started 3D stacking back in 1989 at Thomson. Packages are wafer-to-wafer with silicon vias, and they also stack rebuilt wafers, but with SiP this is difficult since dies come in different sizes, 6, 8 and 12 in., respectively, depending upon the country of origin. So, burning in before stacking becomes important, then cutting using XY-axis cutting on a dicing machine. Then they dip the stacked wafer, stacked height 10-12 in. into the ENIG process, then stack up to 200, etch by laser, turn, and etch other side. Very straightforward. Placement accuracy on the reconstituted wafer is ±7 μm.
Figure 3 Dr Marc Desmulliez (left) from Heriot-Watt University
Dr Marc Desmulliez (Figure 3) is also from Heriot-Watt University and is also interested in 3D manufacturing. The 3D-mintegration (manufacturing in three dimensional surfaces) is the project which he is leading (www.3D-Mintegration.com), and he wanted to talk about three techniques. The first is called depose – this is a new process that permits the optimum filling of via holes, so that any fluids are not trapped, and here a low-deposition rate is employed to give conformal growth applied by megasonic migration which gets rid of the bubbles. A 5:l aspect ratio achievable here. Write – is the second technique – direct writing of metal tracks onto polyimide, or non-metal surfaces. This is a photo-chemical process, so they change the surface of the polyimide surface in a potassium solution, then into silver nitrate, then under a laser beam to create the photochemical process to bring the silver ions onto the surface, upon which you can electroless plate. The last one is called cure – variable frequency microwave curing of encapsulants. By manipulating the electromagnetic field you can vary the radio-frequency behaviour, thus the variable frequency microwave, which provides the same degree of processing but is much quicker, minutes as opposed to hours.
“Vacuum sealed hermetic wafer level packaging technique featuring through wafer interconnects and low temperature direct bond” was the lengthy title of the paper given by the tall James Lee of AML, who is an Engineering man who likes building things. AML produce equipment that is aimed at the smaller end of the market using low-temperature direct bonding. They are developing a suite of process steps – direct bonding, eutectic bonding, gold bonding, glass frit bonding with an interlayer, and thermo-compression bonding. Also CNP for polishing, plasma preparations, etc. They work within the Rutherford Appleton Laboratories at Oxford. Chip-to-wafer and wafer-to-wafer both have benefits and limitations, he listed them all, and added that here vias can be powder blasted, or fabricated by DRIE. The wafer is then oxidised in a furnace, the via is filled with solid Au, and the via wafer is removed from the metallised wafer. Powder blasting limits one to 70 μm, though. Wafers up to 200 mm in size can be handled at AML, and the company is busy enough right now.
After lunch, we listened to news about the first high volume via process for packaging and integration of MEMS/CMOS from Tomas Bauer of Silex. Silex is a MEMS foundry in Stockholm, Sweden. They started up in 2002, and in 2003 made a 6 in. foundry fab. MEMS is still a young industry, and well-qualified people are essential, as they will be able to produce 400,000 8 in. mask layers per annum soon. He described the “Through silicon insulator” technology, which increases functionality. Silicon is a good material for packaging as you can machine it, it can be used towards the trend towards smaller packaging. Making MEMS that have zero crosstalk is one of their innovations, available through wafer “ladder trenches” in mixed signal devices. These ladder pattern trenches provide improved dielectric isolation whilst at the same time reducing the risk of electrical shorts.
Piers Tremlett of Zarlink Semiconductors, and talked about future trends for SiP in Medical Inplant Applications, and here module and package design can be undertaken at their plant at Caldicott, South Wales. Made hybrid thick film products initially for 17 years, but as margins declined they looked at medical equipment as being a good niche market, they now make ceramic chip carriers, and these are used in implants which can be used in a number of places – heart, ear, pacemakers dominate the market, due to arrhythmia. Research projects include shift, chip and adept. Difficulties in embedded components were described, which include demanding accuracies, lack of large area placement machines as well. Shift – this is where one stud bumps the die using gold, but on a flexible substrate so that it can be folded. CiP is based on FR4 core, with plated die wire bonds, and is reliable, being shielded. Planar embedded passive components and integrated thin film passive ICs are also available from Silex.
iMAPS UK have held yet another excellent conference, as always with something for everyone, and a wide range of interesting topics. Andy Longford and his team of colleagues are to be congratulated.
John LingAssociate Editor