TSMC unveils Reference Flow 8.0 to address 45nm design challenges

Citation

(2007), "TSMC unveils Reference Flow 8.0 to address 45nm design challenges", Microelectronics International, Vol. 24 No. 3. https://doi.org/10.1108/mi.2007.21824cad.002

TSMC unveils Reference Flow 8.0 to address 45nm design challenges

TSMC unveils Reference Flow 8.0 to address 45nm design challenges

Lowers entry barriers to designing for TSMC 45nm and other advanced process technologies

Taiwan Semiconductor Manufacturing Company, Ltd has introduced Reference Flow 8.0, the latest generation of the foundry's design methodology that increases yields, lowers risks and improves design margins.

Reference Flow 8.0 supports TSMC's 45nm process technology with advanced standard cell, standard I/O and SRAM compiler. Key features address new design challenges at 45nm, including statistical timing analysis for intra-die variation, automated design for manufacturability (DFM) hot-spot fixing and new dynamic low-power design methodologies.

Reference Flow 8.0 not only supports TSMC's advanced process technologies such as 45, 65 and 90nm, but also provides mature, proven design flows for mainstream technologies from 0.13 to 0.25m.

Reference Flow 8.0 supports TSMC's Active Accuracy Assurance initiative, which defines standards of accuracy for all partners in TSMC's design ecosystem, as well as for TSMC itself. Reference Flow 8.0 focuses on ease of use, providing a reference of qualified design building blocks that give designers a proven path from specification to tape out.

“TSMC's 45nm process technology requires ever-deeper collaborations with EDA vendors and other partners in our design ecosystem,” said Kuo Wu, Deputy Director of design service marketing at TSMC. “Reference Flow 8.0 provides a seamless link between the designers and advanced process technologies, and is supported by TSMC's unrivalled real-world manufacturing technology and capacity”.

Enhanced statistical timing analysis

Reference Flow 7.0 introduced the first foundry design methodology to include inter-die statistical timing analysis to accurately determine the timing effects of manufacturing process variations. Reference Flow 8.0 expands on this capability by offering intra-die statistical timing analysis along with statistical leakage and statistical timing optimization. Statistical leakage provides a more precise analysis of leakage that reflects actual manufacturing outcomes. Statistical timing optimization helps reduce the need for over-design and enables more effective timing closure. These features enable designers to optimize design margins and increase yields.

Design for manufacturability

Reference Flow 8.0 provides further improvements in DFM methodology, which allows designers to address potential manufacturing challenges during the design process, rather than post-processing after tape-out. Among the new features are automated DFM hot spot fixing to eliminate the need for manual correction and DFM electrical variability consideration, which monitors parametric performance shifts caused by DFM effects. Increased automation and integrated analysis and optimization capabilities shorten design cycles by enabling designers to anticipate DFM issues and quickly take necessary measures.

Low power design

Reference Flow 8.0 includes a number of new and innovative power reduction techniques including TSMC's new AVS (Adaptive Voltage Scaling), which enables reduction of active power consumption for next-generation mobile devices. A dual power rail SRAM design enables more dynamic power reduction, and long channel device innovations cut power consumption due to leakage. Coarse- grain power gating and other techniques employed in standard cells further reduce overall standby leakage. The Common Power Format (CPF) enables significant improvement in automated low-power design methodology. Together, these features extend battery life for portable devices and reduce packaging and cooling costs.

For more details contact: www.tsmc.com</a..