Microvias for Low Cost High Density Interconnects

Microelectronics International

ISSN: 1356-5362

Article publication date: 1 April 2003




Willis, B. (2003), "Microvias for Low Cost High Density Interconnects", Microelectronics International, Vol. 20 No. 1. https://doi.org/10.1108/mi.2003.21820aae.004



Emerald Group Publishing Limited

Copyright © 2003, MCB UP Limited

Microvias for Low Cost High Density Interconnects

Microvias for Low Cost High Density Interconnects

John H. Lau and Ricky LeeMcGraw Hill560 pp., 12 chapters, illustrations and photographs

Keywords: Microvias, Inter connection

Lau and Ricky Lee have just produced another timely text book for the industry, which will undoubtedly be well received by design and fabrication engineers alike. The use of microvias of different styles has been growing in the industry for the last few years with many new techniques being used to fabricate ever smaller connections. The team behind the relatively new Professional Engineering Series from McGraw Hill should be congratulated on yet another strong title.

The new text is not exclusively for the PCB fabrication engineer as its title may suggest it covers via technology for board and component level interconnection. Increasingly Ball Grid Array and Chip Scale Packages use microvias to make interconnection between PCB and silicon possible. After all the BGA substrate is just a small thin PCB, but with very fine feature sizes ultimately a necessity. The first chapter sets the scene in the industry with trends and the ever decreasing feature sizes demanded by professional consumer products.

Ricky Lee and John Lau in chapter 3 cover manufacturing, design and reliability aspects of each of the major via types including drilled, laser ablation and photo vias. The text also provides good coverage of the basic printed board fabrication process and where changes may be necessary for different via manufacturing techniques. Of particular interest is the changes in base substrates necessary with laser vias.

As with many other text books today there is also a chapter relating to alternative solders in this case titled “Solders for the Next Generation”. The main issue for engineers is alternatives to lead based alloys and this is covered both from a solder alloy prospective and the effect on area array packages like BGA and WLCSP Wafer Level Chip Scale Package.

Chapter 11 covers the assembly process for Flip Chip and CSP onto the based substrate and features a number of issues relating to underfill. It illustrates some of the mechanical and electrical faults that occur after environmental testing. It also illustrates visual defects and those that can only be found during X-ray or C Scan.

This is a good strong reference book, well illustrated with line drawings, micrographs and product examples and nothing less than I would expect from John Lau.

Bob WillisSMART Group

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