Philips Semiconductors announces a new methodology for designing next-generation silicon system chips

Microelectronics International

ISSN: 1356-5362

Article publication date: 1 August 2000

Keywords

Citation

(2000), "Philips Semiconductors announces a new methodology for designing next-generation silicon system chips", Microelectronics International, Vol. 17 No. 2. https://doi.org/10.1108/mi.2000.21817bad.016

Publisher

:

Emerald Group Publishing Limited

Copyright © 2000, MCB UP Limited


Philips Semiconductors announces a new methodology for designing next-generation silicon system chips

Keywords Philips Semiconductors, Design, Semiconductors, Silicone

Philips Semiconductors announced its Sea-of-IPTM - a new design methodology for creating the complex, processor driven, silicon chips that will lie at the heart of next-generation consumer products such as advanced set-top-boxes, home networks, automotive systems and 3G (3rd generation) mobile phones. Because they condense all the electronics required in an application onto a single piece of silicon, these new chips are termed system-on-chip (SoC) solutions. They are characterized by the conflicting requirements of ever increasing processing power and system complexity on the one hand, and the need to develop them in much shorter timescales on the other.

Philips Semiconductors' Sea-of-IPTM methodology overcomes this conflict by eliminating the need for detailed knowledge of the electronic circuits (data registers, logic gates, transistors, etc.) that make up the chip. Instead, it provides designers with pre-developed and pre-tested functional blocks known as IP (intellectual property) blocks - for example, a complete microprocessor or networking interface - that they can integrate alongside each other onto a single piece of silicon to create right-first-time system-on-chip solutions. The key to success is having the right IP blocks and system architectures to suit the designer's application, and the right tools to make the design process as simple as possible.

"In future, IP will become the essential condition for doing global business',' said Theo Claasen, chief technology officer, Philips Semiconductors. "OEMs will no longer choose their silicon suppliers purely on the grounds of semiconductor process technologies, design flows and manufacturing capability, but on how closely a silicon supplier's IP portfolio aligns with their own product roadmaps."

Philips Semiconductors' system-level expertise in digital audio, video and mobile communications, significantly enhanced by its recent merger with VLSI Technology, has already placed the company in a leadership position in consumer, multimedia and wireless communications markets. This same expertise is now being used to develop an IP portfolio for its Sea-of-IPTM chip design methodology that will facilitate development of the digital convergence products needed to bring fully interactive multimedia services to home, office and mobile users. The company's NexperiaTM Silicon System Platforms provide application oriented system architectures that can be exploited using the Sea-of-IPTM design methodology to produce high-performance system-on-chip solutions.

To deliver its IP portfolio manageably into the hands of chip designers, the company is leveraging two very powerful design tools developed by VLSI Technology. Through an easy-to-use graphical user interface, VLSI's HDL-i (high-level description language integrator) provides designers with all the information they need about individual IP blocks, plus the ability to modify these blocks for optimum system performance. At the same time, VLSI's VelocityTM rapid silicon prototyping tool allows designers to prototype their designs using fully tested IP blocks provided on special prototyping chips. As a result, hardware and software development can start in parallel, greatly shortening time-to-market for new system-on-chip designs.

Philips Semiconductors' Sea-of-IP® design methodology is targeted for its 0.18 micron CMOS process, and will soon be migrated to 0.12 micron CMOS. The company also plans to incorporate IP blocks for its advanced QUBiC3 and QUBiC4 RF BiCMOS processes. With a process roadmap now accelerated in line with the ITRS (International Technology Roadmap for Semiconductors), Philips Semiconductors will deliver its Sea-of-IP® into state-of-the-art system-on-chip silicon solutions.

For further information about this release please contact: Philips Semiconductors, Eindhoven, The Netherlands. Tel +31 40 2722091; Fax +31 40 2724825; E-mail: Marijke.Sas@philips.com