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Technology news from Philips Semiconductors
Keywords Philips Semiconductors, Design
Philips Semiconductors leverages VLSI Velocity RSP to deliver a hardware/software co-design environment for its Nexperia Silicon System Platforms:
By providing its entire IP portfolio in the form of a single prototyping chip on which IC designers can activate only the IP blocks they require, VLSI Velocity RSP (rapid silicon prototyping) system is a key factor in creating some of the world's most advanced ASICs. Today, the increasing amount of system-level IP that has resulted from the merger of Philips Semiconductors and VLSI Technology has led to the introduction of a new platform-oriented Velocity concept.
Philips Semiconductors, an affiliate of Royal Philips Electronics, today announced the development of the company's next-generation system-on-chip (SoC) prototyping system, currently code-named NAPA (NexperiaTM advanced prototyping architecture). NAPA will allow designers to prototype SoC designs within an application-oriented platform architecture. This is similar to the company's Nexperia silicon system platform methodology to group IP together under architectural frameworks that maximize overall system performance. The announcement was made as part of the keynote address by Theo Claasen, chief technology officer, Philips Semiconductors, at the IP 2000 Design Conference.
"NAPA will allow design teams that use our silicon system platform approach to develop their hardware and software in parallel at system level", said Claasen, "creating real advantage in time-to-market".
NAPA builds on the VLSI VelocityTM RSP concept to provide designers with a hardware/software co-design environment that is application-oriented rather than generic. In addition, NAPA will allow easier upgrading or addition of processors and peripherals, rapid deployment of new process technologies into the prototyping environment, and the ability to deliver far more complex IP blocks.
The volume and complexity of IP blocks in the merged Philips Semiconductors and VLSI Technology libraries make it increasingly difficult to put the entire IP portfolio onto a single piece of silicon. NAPA overcomes this problem by first selecting the natural choice of IP for a particular Nexperia platform. Then, by inserting appropriate bus bridges and high-speed realtime data tunnels, it breaks the IP down into separate CPU, DSP, and peripheral ICs which can be upgraded without compromising system integrity. These ICs are then placed on plug-in prototyping boards that allow the same mixing and matching of CPU and DSP cores as the corresponding Nexperia silicon system platform.
Using NAPA, designers will be able to connect together a set of boards containing a superset of all the IP blocks likely to be needed in their application. By selectively disabling the blocks that they don't need, they will be able to produce prototyping systems that closely mimic their target SoC solutions. If necessary, they can even add their own IP blocks in the form of FPGAs. Through use of the bus bridges and tunnels, the different NAPA silicon prototypes can all be plugged into a single backplane that also allows probing and logic analyzer connections.
NAPA will give Philips Semiconductors the advantage to deliver larger and much more specialist IP blocks into the hands of its customers by placing them on dedicated boards. This creates the ability to develop far more complex SoCs. NAPA will also facilitate the prototyping of the heterogeneous mixes of application specific platforms for future digital convergence products that combine audio, video, graphics and telecommunications functions in a single chip.