Enabling Technologies for Low‐count Chip Packaging

Abstract

This paper explores the enabling technologies and thermal performance trade‐offs associated with inserting small multichip modules (MCMs) into surface mount packages. Using assembly and interconnect technologies available today, ‘few‐chip’ packages can lead to less costly solutions than traditional single chip package approaches, and may be practical depending on system size and modularity constraints. The key enabling technologies required include fine‐line interconnect substrate technology, direct leadframe attachment and chip bonding to fine‐line laminate substrates, the moulding of large substrates with multiple components in a thin surface mount package, and cost‐effective cooling techniques. The thermal performance of a moulded few‐chip package is analysed and cooling methods are discussed. A screening experiment was performed in which several geometric and material parameters were studied to determine their impact on thermal performance. The size of the heat slugs appears to be the variable with the greatest effect on thermal performance. The effects of external board size, board material and the design of the internal substrate on the thermal performance of a few‐chip packaqe are also discussed.

Citation

Hashemi, H., Olla, M., Spooner, C. and Walshak, D. (1994), "Enabling Technologies for Low‐count Chip Packaging", Circuit World, Vol. 20 No. 4, pp. 4-7. https://doi.org/10.1108/eb046268