Enhanced Static Problems with Reduced MOS Chip Geometry

Abstract

The escalating problem of electrostatic discharge damage to MOS devices, resulting from the need for a continual reduction in chip geometry, is examined, with data provided on the range of ESD susceptibility for various component families. It will clearly be of benefit to implement measures that will offer long‐term protection against device degradation.

Citation

Molyneux Child, J.W. (1983), "Enhanced Static Problems with Reduced MOS Chip Geometry", Microelectronics International, Vol. 1 No. 2, pp. 34-34. https://doi.org/10.1108/eb044130