A Heuristic Approach to Placement Sequence Identification for SMT

Abstract

Surface mount technology (SMT) is being increasingly used in printed circuit board (PCB) assembly. The reduced lead pitch of surface mount components coupled with their increased lead count and packing densities have made it imperative that automated placement methods be used. However, the SMT placement process is often a bottleneck in surface mount manufacturing. A reduction in placement time in SMT will enhance throughput and productivity. This paper describes the design and development of a prototype expert system based approach which identifies ‘near’ optimal placement sequences for surface mount PCBs in (almost) realtime. The software structure used integrates a knowledge based system with an optimisation module. PROLOG is the language used in this research. The system was rigorously validated and tested. Ideas for further research are also presented.

Citation

Shin, W., Srihari, K., Adriance, J. and Westby, G. (1993), "A Heuristic Approach to Placement Sequence Identification for SMT", Soldering & Surface Mount Technology, Vol. 5 No. 2, pp. 20-24. https://doi.org/10.1108/eb037823