A VLSI Systolic Implementation of a String Pattern Matcher — Part II

Abstract

In Part I surveys of the architectural concepts involved in designing special purpose VLSI computing structures and systolic array, WARP and CHIP architectures and their applications were discussed. The INMOS transputer chip and the parallel language OCCAM were also introduced. In Part II the soft simulation of systolic algorithms via OCCAM programs is considered with particular reference to their constraints and classification. Finally, the systolisation of the pattern matching problem is discussed together with various soft systolic string matcher chip designs and their simulation.

Citation

Evans, D.J. and Ghanemi, S. (1989), "A VLSI Systolic Implementation of a String Pattern Matcher — Part II", Kybernetes, Vol. 18 No. 3, pp. 32-47. https://doi.org/10.1108/eb005819