To read this content please select one of the options below:

A VLSI Systolic Implementation of a String Pattern Matcher — Part I

D.J. Evans (Loughborough University of Technology, Leicestershire, UK)
S. Ghanemi (Loughborough University of Technology, Leicestershire, UK Dr. Ghanemi is now at the University of Annaba, Algeria)

Kybernetes

ISSN: 0368-492X

Article publication date: 1 February 1989

27

Abstract

In Part I of this article, surveys of the architectural concepts involved in designing special‐purpose VLSI computing structures are given. This leads to a discussion of systolic array, wavefront array, WARP and CHiP architectures and their applications. The INMOS transputer chip design and the parallel language OCCAM are introduced. The authors believe that together they form a modular hardware/software component of the type which is essential in the construction of highly parallel computer systems. (Part II of this article will consider the soft simulation of systolic algorithms via OCCAM and the systolisaion of the pattern matching problem).

Keywords

Citation

Evans, D.J. and Ghanemi, S. (1989), "A VLSI Systolic Implementation of a String Pattern Matcher — Part I", Kybernetes, Vol. 18 No. 2, pp. 47-61. https://doi.org/10.1108/eb005814

Publisher

:

MCB UP Ltd

Copyright © 1989, MCB UP Limited

Related articles