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Copyright © 2012, Emerald Group Publishing Limited
13th JISSO International Council Meeting – Nurnberg, MAY 2012
Article Type: Exhibitions and conferences From: Circuit World, Volume 38, Issue 4
Introduction: JISSO is an international council comprising JNAC, IPC, JEDEC, iNEMI, JEC, EIPC, EECA, JISSO JAPAN, JEITA, JPCA and JARA. The purpose of this council is to promote a strategic partnership among global organizations interested in the total solution for interconnecting, assembling, packaging, mounting, and integrating system design. To accomplish these objectives, members will cooperatively work: to support and encourage standards development at a national or international level, to encourage the development of technology roadmaps, to address environmental issues, and to monitor market trends. These activities will be based on the principles of free enterprise, cooperation, and will be undertaken in a spirit of responsibility to the worldwide electronics industry.
Hosted and organised by the EIPC, the 13th JISSO International Council Meeting was held in the Congress Centre at Nürnberg Messe, Germany on 7-9 May. Attended by members from all corners of the globe, the event was chaired by Mr Michael Weinhold, EIPC Technical Director.
TG1-1 The first paper of the three day event was, understandably, the province of Dieter Bergman, who wanted to look at “The Status of Standardisation”, a subject that is sufficiently complex to warrant a guide such as Mr Bergman.
JEDEC, EIA, JPCA, JEITA, DIN, IEEE and ASTM were global standard developers supported by industry, and IEC and ISO were country supported. What the industry needs are may be summarised as:
standards and technical documentation;
a timely consensus by technical experts meeting meaningful requirements;
test methods must be repeatable; and
setting standards is a process that lets many participate.
The strategy is OEM driven.
He illustrated examples of technology sharing, where IPC and JPCA standards had been adopted by IEC, although the history of IEC and IEEE getting together had been difficult in the beginning. There were now dual logo documents in existence, which, he felt, enabled a healthy blend of technical, national, regional, and international standards, and sends a strong and clear message to industry that the major technical standards developing organizations aim to cooperate toward one standard in the world wherever possible. It is an example of sustained effort by the IEC to follow new positions of the WTO/BTB activity: openness, transparency, due process, coherence, market relevance, and from a market and trade perspective, it symbolises a loosening of real and perceived barriers.
As in any such organizations, participation in some committees is limited to a few, but TC91 input is now coming from several countries, although trying to get the necessary four participating countries has become more difficult on some subjects. Some IPC committees are going strong, and many new projects are being developed, examples being BGA replacing J-STD-013 (IPC-7095 now at “C”) and a new Flip Chip Document (IPC-7094).
JISSO participation is now more rewarding, and both Embedded and Printed Electronics of considerable interest.
TG1-2 Mr Bergman moved on to discuss “Global Standards Search Engine Requirements.” The purpose is to see what you can do to your web pages to make it more likely for the search engines to display your pages earlier in the search results, as there is little point in having a web site if people cannot find what they are looking for. So, we have to decide on the key words so the content on the site matches the words that the enquirer is requesting, so that when enquirers put a word into, say, Google, as a search engine, that they come up close to the top of the list. The bad news is, you can only optimise a few keywords at a time (6-10 max), but the good news is that we can and should optimise each and every page on the web site for a different, more appropriate, set of keywords.
Mr Bergman outlined the three digit digital object identifier (DOI), wherein the first digit follows the JISSO levels, and the second digit follows nine categories – administration, design, materials, pre-manufactured parts, mounting and interconnecting processes, mounting product function and performance, assembly processes (includes diffusion into silicon), assembled product performance, and lastly quality reliability and testing.
The third digit is based on the technology. The documents themselves should have a document number, the date of publication and revision level if applicable, note on size as in page count or computer storage in megabytes; a DOI; key words; a document description (75 words or less – credible and distinct); owner description and link to owners page; e-mail address to contact owner – date of information entry; status of document and availability, and an indication of the value to customer as determined by the owner.
TG1-3 Mr Minsu Lee of the Advanced Technology Team in the R&D Centre of the Doosan Corporation shared his thoughts on “the need for standardisation of printed electronics.”
He gave an introduction to the process, the many advantages, the materials and the applications, or end use. By 2020, the market for printed electronics is estimated to be worth $30 billion; about one-third will be in display, the other split between lighting, smart products, energy, etc. He examined the comparisons between printed electronics, and semi-conductors in terms of reliability, stability, before setting out the areas in which standardisation is required.
Related standards were shown, IEEE have Standard P1620TM-2004 for Test Methods for the Characterization of Organic Transistors and Materials; IEC have TC113, and are developing IEC 62565-3-2: which covers nano-manufacturing-material specifications – Part 3-2: Graphene – detail specification for nano-ink.
IPC have IPC-4921 Requirements for Printed Electronics Base Materials (Substrate), IPC-4591 Requirements for Printed Electronics Functional Materials and IPC-6901 Performance Requirements for Printed Electronics Assemblies and IPC-2291 Design Guidelines for Printed Electronics.
Standards will cover terminology, materials, instrument specification and operation, and standardising processes. All of these will be covered by the TC119 working group, with WG1 looking at: terminology and nomenclature, WG2: material characterisation, WG3: equipment, WG4: printability, WG5: products (material, devices, matching technologies) and WG6: environment, health and safety (EHS).
TG1-4a Mr Walter Huck presented a paper giving the present status on the development of national and international standards for embedded device technology.
Global activity on device-embedded substrates is going apace; IEC TC91 – assembly technology have started five projects; in Germany DKE K682.0.5 working group started in September 2010, they have held four web meetings, the first of these in May 2011, and has Bosch, EIPC, Fraunhofer IZM, KSG, Murata, NXP, Schweizer, Taube Elektronik and Würth as members.
JPCA has their JPCA-EB01 (2011) Standard on Device Embedded Substrate – Terminology/Reliability Test/Design Guide, and JEITA has formed its own embedded components task force. In the states, IPC has formed the D-55 Embedded Devices Process Implementation Subcommittee, to prepare IPC 7092 – Design and Assembly Process Implementation for Embedded Components.
IEC Device Embedded Substrate Projects include IEC 62326-15 General electrical test guide for device embedded substrate with active devices, passive components (capacitor, resistor inductor, etc.) integrated passive devices (IPD) and discrete packages, in which a draft is under way. The project has determined the test probes and patterns for testing, and the testing process.
A draft of IEC/TS 62326-16 Generic specification is under discussion. IEC/TS 62326-17 test element group (TEG) has had new work approved, and a draft is to be discussed.
The same situation pertains to IEC 62326-18 Test Method and IEC 62326-19 Design Guide, but here the draft is under preparation based on IEC/PAS 62326-14, which was withdrawn. It was deemed prudent to use existing methods rather than inventing new ones, and only what is specific for embedded substrate technology should become an international standard.
Requirements to components for embedding could become IEC 61760-5 (PNW), and would include such specifics as dimensions, stand-off, tolerances, metallization material, surface condition and thickness. Components had to have mechanical strength, to withstand the insertion process, the laminating process, board assembly and the handling process. They would need temperature resistance, to withstand laminating and soldering; chemical resistance to withstand the etching and plating processes; and sensitivity aganst laser, ESD, and thermal mangement.
TG1-4b – the status on the development of national and international standards for embedded device technology; terms and definitions of embedded device technology was reported upon by Mr Hisao Kasuga, of IS-INOTEK (International Standards – Innovation Technology Research Association).
International standards – this is IEC 60194: printed board design, manufacture and assembly – terms and definitions. Other individual standards are covered by TC91.
Industrial standards are:
IPC-T 50: Terms and Definitions for Interconnecting and Packaging Electronic Circuits; and
JEITA(EJAJ) ETR-7001: Terms and definitions for Surface Mounting Technology, JPCA-TD01-2008: Terms and definitions for printed circuits, JPCA-EB01-2011: Standard on Device Embedded Substrate Terminology/Reliability Test/Design Guide – Edition 4.
Based on JPCA-EB01-2011, the future IEC 62326-14: Printed boards – Device Embedded Substrate – Terminology/Reliability/Design Guide was introduced as 91/894A/NP in 2009, and now split to; Future IEC/TS 62326-16: Printed boards-Device Embedded Substrate-Scope and Definition. Future IEC/TS 62326-17: Printed boards-Device Embedded Substrate-TEG. Future IEC 62326-18: Printed boards-Device Embedded Substrate-Test Method, and finally the Future IEC/TS 62326-19: Printed boards-Device Embedded Substrate-Design Guide.
IPC – 7092 covers the design and assembly process implementation for embedded components.
Mr Kasuga suggested ways in which the harmonisation of TC91 could be implemented. This would be to quote the technically specific “terms and definitions” standardised by the specific TC’s. Assemblies: TC91, PWB: TC91 (TC52), Semiconductors: TC47 SC47D, etc. Passive components: TC40, etc. Use/list all of “terms and definitions” used by the TC’s, if they are used in different meanings. Try to unify all of “terms and definitions” used by the TC’s, if they are used in the same meanings. Propose the “terms and definitions” summarized in the above way as TR/INF in TC91WG6, then propose the result of “terms and definitions” summarized by relevant TC’s as IS to TC91WG5.
Actions would include:
Each relevant TC is to be assigned as a responsible TC to adopt necessary “terms and definitions” into draft TR.
Each “terms and definitions” is to be reviewed by each responsible TC: comparison table is to be prepared.
All “terms and definitions” listed in the comparison table is to be reviewed and fixed according to the policy.
All “terms and definitions” of WG6 is to be proposed to TC91WG5 for update of IEC 60194.
Here the level of importance can be defined as follows: AAA: most; AA: fairly; A : average, and X : to be deleted. Other necessary “terms and definitions” is to be added from JPCA-EB01-2011 and others.
Responsible IEC/TCs are to be assigned to collaborate to review each of the terms and definitions, as follows: JISSO (assemblies): TC91; PWB: TC91(the former TC52); semiconductor devices: TC47; semiconductor PKGs: SC47D; passive components : TC40, and connectors: SC48B.
TG-2-1. Reviewing the “Technology challenges in packaging technology” occupied the time of Mr Hirofumi Nakajima of Renesas Electronics Co. Bonding methods have been diversified, varying from wire, face-to-face, PoP, flip-chip, wireless and TSV bonding according to device requirements. It is recognised that bonding methods are the limiting factor of electrical performance, which is why Cu-wire bonding has been expanding in production for consumer products packaged in FBGA, HQFP, SiP, etc. in Renesas.
Wire bonding for high-temperature applications is vital. LSIs that tolerate 150°C of maximum ambient temperature are available now, but, said Mr Nakajima, we must prepare for an increase to 175°C in ambient temperature. Copper wire bonding is more stable at high temperature than gold wire bonding because of slower growth rate of copper-aluminium intermetallic compound (IMC).
Flip-chip applications are rapidly increasing and diversifying. The bump-pitch-pitch roadmap depends on applications, such as low cost, handheld, and high-performance devices. With reducing bump pitch, solder bumps for some applications will be substituted by Cu pillars.
This year has seen significant advancement in semiconductor-package technologies, but some challenges remain in interconnection: how to expand Cu-wire production, the need for a robust under-pad structure, accurate control of Cu wire diameter, – replacing solder bumps with copper pillars, structure design of bump/pillar resilient to stress, a less stress-generating process, applicable to wideband communication and larger memory capacity, with solutions for higher thermal density.
TG2-2 – “TSV Interposer Technology in North America” was described by Mr Vernon Solberg, who explained that the adoption of TSV (through-silicon-vias) technology was being driven by the need for a smaller package size-to-function ratio, higher operating performance, the call for reduced power consumption, and a lowering of the semiconductor packaging cost.
Wireless and portable electronics continues to dominate a wide number of market segments. Due to the insatiable consumer demand for complex applications, smart phones and other personal electronic products have an increasing need for greater component functionality, increased data storage and lower power.
The challenges are to provide 5 μm double-sided re-distributed layers (RDL) on ultra-thin glass and silicon panels with 10X lower signal loss than the oxide-lined TSV interposers. To produce multi-level RDL with 3 μm lines and spaces and 5 μm vias and Cu-to-Cu chip-to-interposer interconnections at 15-50 μm pitch. Perfect the process for embedding high performance thin-film passives such as IPDs on thin planar layers, and develop module demonstrators in power, analog, digital, RF, mm-wave, MEMS and LED packaging applications.
The TSV dedicated foundry evolution was highlighted; here a number of US companies have established foundries that specialise in furnishing expanded wafer process services such as via ablation, plating, thinning and RDL and passivation.
The infrastructure for TSV was expanding, and semiconductor package assembly and test service providers have expanded their capability for wafer level processing as well.
TG2-3 “3D Approaches for Heterogeneous System Integration” were illustrated by Mr Jürgen Wolf, of Fraunhofer IZM. 3D is performance driven, given the need for the highest integration density, reduced interconnect length, improved signal transmission speed/bandwidth, and reduced power consumption functionality will include multi device integration (AD SP), sensor (MEMS), transceiver memory and processor. Form-factor drives include mobile communications, ID cards and the inevitable cost reduction. The main applications for 3D integration will be digital SiP, digital analog SiP memory, wireless, image sensors, MEMS/sensors/opto, and power.
3D integration requires its own technology path, has its own specific solutions, timeline, and infrastructure. The Fraunhofer IZM vision is to integrate heterogeneous chip functionalities in one package by using enhanced 3D integration, assembly and interconnect technologies. This will include the development of leading edge technologies for WLP and 3D-WL system integration, the provision of customised solutions for product integration and process transfer, supporting equipment and material evaluation for the supplier, and prototyping and manufacturing using qualified processes on a latest state of the art process line (200/300 mm) for WL packaging, and 3D-WL system integration.
TG2-4 3D standards were discussed by Dieter Bergman, who felt that this is a team game. The members would ideally include successful design and assembly of complex, fine-pitch circuit boards and assemblies, and would comprise the device suppliers (it maybe one, or many), the interposer designer and supplier, the assembler, the material suppliers (different interconnects, different TSVs, different device thicknesses will need different materials, such as underfill, solder, epoxy, etc.) and ideally an understanding brewer, to alleviate the stresses.
The EDA industry, in the coming years, should develop a better understanding of the different types of TSVs, e.g. Tungsten vs Copper, TSV processes (first, middle, last, hidden vs through), and the trace metal differences (FEOL vs BEOL, vs HDI PCB). It should co-ordinate with the assembly equipment suppliers to create an acceptable file exchange to program device registration and placement. The creation of databases of the design guidelines would help define the selection of assembly processes, equipment, and materials. It should encourage and participate in the creation of standards, such as workmanship, which drive both design and assembly tool development.
Dieter traced the history of The Surface Mount Council and its formation back in 1987, and the work that it has done since. There is some discussion on the formation of a new Council, for which a meeting is proposed in September 2012, in the week of CICC, in San Jose. Matters for consideration would include the level of interest in participation, the impact of JIC activity, the relationship of standards bodies, that US government funding is available, and the level of management participation. He would like it all to start this year and expand in 2013.
TG3-1 – the session on 8 May commenced with a presentation by Mr Thomas Hofmann, of Hofmann Leiterplatten GmbH entitled “Developments in embedded components”. He clarified the understanding of what embedded components are; this means active or passive components on the inner layer of PCBs, using available but different embedding technologies. The first patented technology to embed SMD components in a PCB was the AML® technology back in 1996. The advantages of embedded components are that they offer protection against environmental influences, permit the miniaturization of multilayer assembly, improve the electrical properties (EMC) and offer an improvement in the thermal properties. The driving forces behind embedded components are the automotive (e-mobility) and lighting (LED-lighting) sectors, as conventional packaging and interconnection technologies can offer no further increase in power density.
Mr Hofmann illustrated several examples of test panels for assessing the thermal properties and the results obtained. Combining embedded components with heat sinks dramatically reduces the board temperatures. The applications were varied. In the field of sensors, sensor housings are now completely replaced by the circuit board, and with the electronics protected within the printed circuit board housing they can be used in aggressive environments. This applies to level sensors, proximity sensors, temperature sensors, position sensors, capacitive or inductive proximity sensors.
They have successfully integrated a USB controller, temperature measuring device, resonator, resistors and LEDs into a circuit board for use in traffic light simulation, with a final thickness of only 3.0 mm. He illustrated examples of boards with embedded components being used in the automotive lighting field, and in the formation of modules with BGAs (System In PCB, or SiPCB), with the advantages that recurring units (parts) can be used multiple times, there is faster development of modules, with consequent cost savings.
Embedded components in circuit boards offer the advantages of smaller dimensions through multi-layer assembly, the protection of electronics from environmental influences, higher reliability due to uniform heat distribution, improved thermal management of components, better thermal connection of the components, lower component temperatures, and a resultant longer lifetime.
TG3-2 Painting the picture for “Embedded components in circuitry within Europe” was the subject of Mr Michael Weinhold of EIPC, who reflected upon the changes that has taken place. Whereas there were 425 PCB manufacturers in Europe in 2008, now there are just 280, with another possible 100 in Russia. However, Europe as a market comprises 27 countries, and 495 million people, putting the EU in third place after China (1,322 million) and India (1,130 million). There are various projects running in Europe which are aiming towards finer resolution, IPITECH (Innovative PCB Integration Technologies for HDI Boards in Harsh Environment) with the following objectives:
Assess, adapt and validate new high density PCB technologies in harsh environment.
Copper filled micro vias, stacked-micro vias, micro vias-in-pad, track width: 75 and 50 μm locally.
Assess the impact of these new technologies on signal integrity and thermal management.
Assess the mounting of new passive and active packages.
With the embedded component market projected to be worth €600 million by 2015, that there are some major names involved comes as no surprise. Another project is entitled HERMES, an acronym for high density integration by embedding chips for reduced size modules and electronic systems, which involves companies such as AT&S, Siemens, Fraunhofer, Bosch, Infineon, IMEC, Thales, Atotech and Circuit Foil, Luxembourg. Michael reminded the delegates of the intrinsic perils of soldering, and compared these with the new system in PCB which made it possible for advanced embedded devices including the connectors in PCBs, sensitive components as well as batteries and displays, with low profile design, space improvement for component placement, and the embedding of pressure sensitive components like sensors. That it would be possible to increase packaging density and improve EMI shielding as well would be very advantageous.
TG3-3 Mr Hajime Tomokae of Fukuoka University has been involved with the research and standards through a national project on SiPs supported by their Ministry of Science and Education. Phase 1 ran from 2002 to 2007, involving 0.5B\/yr, five groups, one is SiP group, a consortium of nine companies; an EDA tool STEERSIP, with SELBIC and TDR tester for evaluation. Phase 2 started in 2007, and continues; comprising 1.8B\/yr, 22 groups, and the biggest group is the SiP group, a consortium of 14 companies, with MEMS/SiP EDA tool STEERMEMS, TEG chips with low-k materials and TSV, and evaluation equipment MEMS wafer tester. STEERSIP is a standard for electromagnetic, thermal analysis and co-design, commercially available in Japan; STEERMEMS covers stress analysis (adventure cluster) added, total MEMS package analysis and is now on Version 5.0. There is a new data format with the name of FUJIKO, which is 3D data format for device embedded substrate, and there is FUJIKO Ver.1.0 for JPCA standard EB02 (Edition 1).
Mr Tomokae showed the new Research Center for 3D Semiconductors which opened at Fukuoka University in March last year, 600 × 500 lithography, which had had some impressive results after their first year in operation. Concluding his presentation, he reminded the members that there has been a JPCA standard on device embedded substrates since 2008, EB-2 (Edition 1) was published in November 2011, and EB-01 (Edition 5) will be published in June this year. He is always open to discussion on device embedded substrates involving the 3D structure of embedded components, and the establishment of a standard.
TG3-4 “Embedded technology for MLCC” was the subject of a paper from Mr M. Tamba of Murata Manufacturing Co. In a well-illustrated presentation, Mr Tamba was able to demonstrate that resistance to bending substrate at an embedded component is much better than for surface mounting, that there was no deterioration after desmear, no deterioration after reflow soldering, 250°C/50 s; that there was no deterioration after a thermal shock cycle involving −55°C⇔125°C 5,000 cycles, with a moisture load of 85°C 85 per cent RH for 4,000 h.
TG3-5 Mr Vernon Solberg of Invensas spoke about “Embedded components in circuit boards in North America.” The use of embedded components can reduce assembly costs, enable a reduction board area, and can minimise the cost of purchasing and handling significant numbers of discrete passive components. These economic advantages must, however, consider the higher per unit area cost of PC boards fabricated with embedded component elements. He cautioned that users must also address potential decreases in throughput and overall process yield of the embedded passive and active PCB. Embedding resistors reduces assembly complexity, provides a shorter circuit interface, enables PCB outline reduction, and improves electrical performance.
The application-specific costs depend on many effects when embedded passives are present in a printed board: these include a decrease in printed board area due to a reduction in the number of discrete passive components; lower wiring density due to the integration of resistors and bypass capacitors within the printed board; simplified assembly process; reduced assembly costs and decreased assembly-level rework.
Mr Solberg advised that embedding the semiconductor is where many companies may find a significant roadblock for several reasons – the procurement of semiconductors in a wafer format, the outsourcing of metallization and thinning, and the testing embedded mixed function assemblies. The PCB fabricator cannot perform a full functional electrical test of the end product at the substrate level, so – how to test, what to test and what features are needed to enable test? Ideally, the originating companies will bring together the two primary suppliers; the circuit board fabrication specialist and the assembly service provider.
In North America there is a well-established embedded PCB supply chain in existence, and the Sub-committee working on IPC-7092 – Design and Assembly Process Implementation for Embedded Components comprises no less than 30 distinguished members.
TG4-1 Mr Dennis Fritz of MacDermid introduced the members to his “Status Update for Opto-electronics in the US”. The 2011 iNEMI roadmap shows that the known methods of increasing the amount of data that can be transmitted through installed fibre used in telecommunications will be reached by about 2018. To increase capacity further will require installing and provisioning more fibre, which is an expensive solution. Thus, the roadmap regards the need for more Gbs per fibre in 2018 as an as yet unmet technical need. He showed a graph which indicated that by 2020, traffic will exceed capacity, and things will just grind to a halt.
The answer lies in optical interconnect, and plastic optical fibre. Indeed, optical interconnect technology could change the way PCBs are designed, and current research includes interconnects between chips and within boards. A single optical interconnect could replace 1,000 copper traces carrying voice-quality signals on a board, and the technology reduces power requirements, improves electro-magnetic interference performance and simplifies PCB design. Time it would appear is not on the side of the industry.
TG4-2 “Portable printed electronics applications” were described by Mr Marc Carter from the IPC. There are three classes of printed electronics hardware:
Devices – passive (resistors, capacitors, inductors) and active (thin film transistors and OMEMs).
Modules and units – display (emissive, reflective), lighting (OLED, EL), power (primary, secondary).
Final products – Bluetooth headset, structural health monitoring Appliqué.
Passive devices consisted of a single printed layer and one processing step to fabricate resistors, membrane switches, etc. There was a minimal risk for manufacturing yield. Active devices comprised multiple printed layers and at least five processing steps requiring registration and resolution control to fabricate an active matrix pixel driver for emissive and reflective displays. Increase in manufacturing complexity demands greater process control.
Displays – several advanced materials, e.g. electro-optic, reflective/emissive, semiconductor. Low manufacturing risk; greatest risk associated with material performance.
Lighting – multiple materials electro-optic, OLED/ILED, electroluminescent. Low manufacturing risk; greatest risk associated with material performance.
Logic/memory – novel materials systems. Low manufacturing risk; highest risks are market acceptance and cost.
RFID – high performance semiconductor materials. Moderate manufacturing risk; highest risks are cost and in-field performance.
There are some gaps which need to be addressed, these include – supply chain: design software, materials, manufacturing platforms, testing tools; in-field performance: devices, modules and units, and final products; infrastructure: standards, roadmaps, and trade associations.
TG4-3 “Printed Electronics in Korea” is in a mature state, and according to Mr Minsu Lee of Doosan Corporation will be worth $30 billion. The biggest sector of this market will be in display, which dwarfs all others. Printed Electronics was introduced to Korean industry through display technology from early 2000, and now with the development of nanotechnology, there has been much work on nano-materials for ink, and the roll to roll process is the main focus for the printing equipment industry. Korea is the IEC TC119 (Printed Electronics) secretariat. He very modestly stated that Korea is a leader in PE related industries, display and mobile device especially, and has advanced technology in equipment and materials as well as engineering expertise in adapting PE technology for mass production. The famous names which appear, along with the very substantial Government funding for the myriad organizations involved in the PE field, and from the depth of his presentation it can be seen that his claims for prominence in the market are fully justifiable.
TG4-4 “Advances in Printed Electronics” was the subject of the final presentation of the day from Mr Katsuaki Suganuma of Osaka University. Why PE now? He asked. The answers were many – no one can stop the price of digital equipment falling, and with short product cycles there is a large risk for infrastructure investment. There are strong demands for thin and large electronics – in the fields of TV, solar, lighting, and wireless connection and memory is everywhere. PE can be wearable, stretchable, apply to healthcare devices; there is a huge market for ultra-low price electronics. PE does not need electricity, but they do need affordable flex solar/battery. For the eco-warriors, PE contains no toxic element, is rare earth-less, and requires low energy in production.
Expanding on the ECO theme, Mr Suganuma said that it was now estimated that E-paper news delivery eliminates 4,700 newspapers a day, which means the protection of forests and a 5.2 per cent reduction of CO2 emission. PE is rare earth metal free – PEDOT and Ag nano-network makes TCF without ITO. A low energy process, 100°C-150°C compared to Si devices beyond 1,000°C → below 200°C, and without soldering at 250°C → 100°C.
Mass-production and cheapness, for anywhere and everyone. Mr Suganuma gave the meeting a long look at the various applications, the areas of increasing demand, and how PE was produced, especially with printed batteries. Printed electronics are, he emphasised, here now and here to stay. Low temperature curable metallic nano-inks, even room temperature sintering wiring, are available. Ag nanorods become TCF at room temperature, and conductive adhesives have been expanding their applications into new PE products. Room temperature bonding can be possible. Standardisations have begun at ICE, ISO and IPC. A series for ICA testing methods is proposed for ISO standardisation.
John LingAssociate Editor