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Emerald Group Publishing Limited
Copyright © 2011, Emerald Group Publishing Limited
IC package innovation: choosing the right solution TWI, Granta Park, Abington, Cambridge, 26 May 2011
Article Type: Exhibitions and conferences From: Circuit World, Volume 37, Issue 4
On May 26, TWI hosted an IC Packaging Innovation Conference at Granta Park that had been organised by the National Microelectronics Institute (NMI) with support from the Innovative Electronics Manufacturing Research Centre (IeMRC). The focus of the event was emerging packaging technologies and it began with an introduction and welcome to the capacity audience by Paul Jarvie from NMI. The keynote presentation was then given by Grace O’Malley of iNEMI and was entitled, ‘Technology trends and roadmaps for packaging innovation”. Grace began with an overview of iNEMI, which was established in 1994. Its mission was to forecast and accelerate improvements in the electronics manufacturing industry for a sustainable future. iNEMI took part in technology roadmapping, collaborative projects and in producing position papers. It had a major focus on the environment, miniaturisation and medical electronics and produced a new roadmap every two years. The 2011 Process Roadmap had recently been published and this had 21 chapters that had received contributions from almost 600 people. Grace then described some of the technology trends that had been identified in the new roadmap. Connectivity was the key to consumer electronics growth and this, in turn, was driving the development of packaging technology. Consumer electronics required lower cost, higher performance and many other features and these meant that there was a continuing need to provide smaller package sizes. System in Package (SiP) was said to be rapidly penetrating most major market segments and, by 2014, it was estimated that there would be 15.9 billion units produced. Three-dimensional integration was also receiving much attention and there were a number of different approaches in use. Through silicon vias (TSVs) would be key to the success of 3D integration, although there were also a number of difficult challenges to be overcome in terms of design, materials, processing and testing. Examples of wafer-level packaging (WLP) and MEMS were also presented and these were now covered in the iNEMI roadmap. Key long-term challenges were then discussed. SiP and WLP were demanding new equipment and there were also many new reliability challenges to be addressed. On the materials side, there was a move to greener alternatives and processes. Warpage was an ongoing problem and it was becoming a primary limiting factor for ball pitch and ball size in fine pitch BGAs.
The second presentation was given by Yann Guillou from ST-Ericsson and was called “Packaging technologies for smartphones: trends, challenges, roadmaps”. Yann began by giving an overview of his company, which was a leading supplier of platforms and semiconductors for wireless devices. The mobile industry was said to be one of the most challenging areas in the electronics arena in terms of performance, integration and cost of packaging. Packaging was becoming a significant percentage of the platform hardware costs and also a key contributor to the overall performance of a device. Co-design was needed between IC packaging and the PCB in order to achieve an optimised system solution. Yann then discussed four of the key enabling packaging technologies. The first was bumping and flip chip and ST-Ericsson had seen exponential growth in the use of flip chip technology in its products. The main drivers were I/O density and the demand for shorter paths to meet performance requirements. The main technologies were solder bumps and copper pillars. With tighter pitches, solder bumping with mass reflow and capillary underfilling were becoming more challenging and new approaches were needed, such as those based on thermocompression. Wafer-level chip scale packaging was finding increasing use in cell phones, as it obviated the need for a laminate substrate and it enabled the smallest footprint on the PCB. Both “fan-in” and “fan-out” approaches were being used, depending on the die size. The “through mold via” approach was also then described, where vias were produced in the moulding compound that enabled die to be stacked on top of each other and connected. Six examples of the next key generation of package on package technologies were also discussed and there were a number of different approaches that had been adopted to solve some of the key challenges such as footprint reduction, thickness reduction, increasing numbers of I/Os and decreasing pitch, etc. The final approach discussed was TSV technology, and this was being driven by the “More than Moore” approach which included heterogeneous integration. TSVs provided an interconnect technology enabling 3D integration at the IC level. They were produced using the process steps of via etching, via filling and wafer thinning and there were different ways to actually produce TSVs. Yann concluded by introducing the so-called “wide I/O interface with TSV” approach, which gave the best bandwidth/power trade off. TSVs were still expensive and there were only limited products in the marketplace at the moment.
The third presentation of the morning was given by Andy Whittaker of TWI Ltd and was on the subject of “IC packaging for harsh environments and testing”. Andy began by stating that packaging needed to catch up with some of the new semiconductor technologies such as silicon carbide and plastic electronics. He then went on to detail the required functions of a practical package and to define what was actually meant by a harsh environment. A harsh environment was defined as having at least one extreme stress from the application that could impact the device lifetime. All conventional packaging materials tended to have some deficiencies, especially as many of the new semiconductor devices were required to operate at very high temperatures that were well above the capabilities of many conventional materials. The thermal capabilities of adhesives and encapsulants were then reviewed and these were also seen to be deficient at the elevated temperatures required for many new applications. A key approach to developing more reliable packages was to reduce the number of joints and to use, for example, integrated passive technology. This approach was being developed in the ongoing TSB supported “PPM2” project. TWI had also done a lot of work in helping to extend the applicability of wire bonding through improved performance and the use of alternative materials. Confocal laser microscopy had been employed to accurately characterise wirebonds. Work had also been carried out to improve adhesives and encapsulants, via the development of organic-inorganic hybrid materials in an approach known as “Vitolane” technology, which was based on silsesquioxane chemistry. These materials had a ceramic core with an organic shell that could be functionalised and examples of the possible different chemical structures were shown. Andy then discussed moisture permeability testing and the approaches that had been used by TWI. Work to improve thermal conductivity using carbon nanotubes was also discussed and key thermal management material selection issues were reviewed.
The final presentation of the morning was given by Larry Zu, the Senior Director of Sales and Engineering at Global Unichip Corporation, who gave a presentation on “The driving force behind today’s packaging technology”. He began by giving an overview of the evolution of semiconductor packaging and pointed out that there was typically a 30-year period from invention to household use. Three-dimensional packaging using TSVs was still five years away from widespread commercial use and would require a major input from the design community. He also described the key performance and cost drivers for packaging technology: with disruptive technologies it was often necessary to show a ten times improvement in performance at no more than double the cost. System in package helped to improve signal integrity, with the exception of RF chips, but a big challenge was heat removal. Larry then showed how the use of TSVs could provide solutions to many of the limitations of current SiP and chip stacking approaches. However, there were still many 3D TSV challenges including the lack of EDA tools, the lack of standards, design complexity, power and thermal issues, assembly and test and the manufacturing costs. He then discussed the use of copper pillars, stating that this technology had been in production since 2006, when it was first used in an Intel “Pentium” processor to overcome electromigration issues. Copper pillars offered a number of advantages, including lower cost, good current carrying capability and pitches of 50 microns were possible. Larry summarised by saying that copper wire was now a viable mature technology for mass production.
Following a networking lunch, the afternoon session had a focus on copper wire bonding and began with a presentation on the industrialisation of fine pitch copper wire bonding by Brad Factor from ASE Europe. The key motivation for moving away from gold to copper had been the increasing cost of gold, although there were many challenges that needed to be addressed if copper was to find widespread use. These included surface oxidation, the need to use forming gas and the hardness of the copper. However, there were also benefits in addition to the reduced cost and these included the higher thermal conductivity of copper. Studies had been undertaken to optimise ball formation with copper. Generally, the process window tended to be narrower for copper than gold. If aluminium pads were used, the optimum thickness was 0.8-1.5 microns, although NiPd pads could also be used. Work had been undertaken to optimise the moulding compounds in terms of reduced chloride content for use with copper wire bonds, because chloride ions reacted with the IMC and degraded bond strength. Copper wire qualification and testing were also described and this included data from accelerated testing studies such as HAST, PCT, HTS, etc. Studies had also been carried out to investigate the growth of intermetallics with copper wire bonding. The use of copper bonding was becoming more and more widespread. ASE had been using 2 mil. copper wire bonding in volume production since 2002. There were 4,300 wire bonders installed by quarter 1 of 2011 and it was anticipated that this would reach 6,700 by the end of 2011. The design challenges for fine pitch were also described and it was stated that the copper ball was wider for a given wire diameter and thus larger bond pad openings were recommended. Multiple die packages were also now in volume production with copper and examples were shown. Brad concluded with a summary of the overall potential and status of copper wire bonding and by stating that it was now spreading from consumer products to automotive applications.
The second paper of the afternoon session was entitled “Transition to copper bonding – an end-user perspective” and was given by Mark Dellow of Picochip Ltd Picochip was described as a fabless semiconductor company that developed semiconductors, software and systems for cellular networks. As was stated in the previous presentation, Picochip were keen to use copper because of the large increases in the price of gold. Copper had better electrical and thermal conductivity, slower intermetallic strength and better rigidity and tensile strength. Copper suffered from oxidation, but this could be reduced by the use of an inert or reducing atmosphere, although palladium coatings on the wire had been developed in 2006 and this approach gave better bond strengths. Issues with copper wire bonding were said to include pad cracking, aluminium splash and reliability but many of these had now been overcome. Picochip had two products in production with copper wire bonding at the start of 2010. Bonding trials had been carried out to optimise the bonding parameters for 50 micron pads. Bond pull and shear strength had been measured for devices exposed to high temperature and thermal cycling conditions and there were no signs of failures for devices bonded with palladium coated copper wire. The recommendation was to carry out an initial set up run with a reasonable quantity of devices to confirm that the performance required could be achieved. For wires thicker than 0.8 mil, the copper wire price was 10-40 per cent less than gold and Picochip had achieved an overall cost saving of 22-30 per cent by switching to copper bonding.
Following the afternoon break, Adrian Dent from Bourns gave a presentation on “copper bonding in opto-package applications”. Bourns had converted their power devices from gold wire to copper. These typically had 16 bond wires and were produced at a rate of millions per week. The company had switched to copper four years ago and had since saved around $1 million. The bond pull strengths for copper had been found to be much higher than for gold. The lead frames used were also copper and Bourns was therefore routinely undertaking copper to copper bonding. A full copper wire bonding qualification trial had been carried out in 2008 and there had been no subsequent reliability issues. Bourns was also planning to convert additional products to copper bonding.
The final formal presentation of the day was by Mark Nichols from Eltek Semiconductor on “Hi reliability packaging”. Eltek provided an assembly and test capability for its customers including a wide range of packaging. Mark began by defining reliability and stated that its absolute definition was not always the same to different people. Some of the potential causes of reliability issues were then described and these were said to include wafer back grinding, die singulation and poor quality probe testing, where pad damage due to heavy probing could lead to subsequent failures. Other factors impacting packaged device reliability included die attach, wire bonding, lid sealing and encapsulation. Mark concluded by saying that it was important to consider the whole process when seeking to provide packaged device reliability.
The final part of the programme was devoted to a panel session entitled “Packaging and the next decade”. This was chaired by David Pedder (TWI) with panellists Martin Goosey (IeMRC), Yann Guillou (ST-Ericsson) and Grace O’Malley (iNEMI) and it involved a detailed interactive discussion of future packaging challenges and areas that would need further research.
In summary, this was an excellent conference with much new, useful and interesting information provided to a large, capacity audience. NMI are to be congratulated for organising such a useful and timely conference.
Martin Goosey26 May 2011