Packaging and Interconnection for Electronics and Sensors – Past, Present and Future

Citation

(2010), "Packaging and Interconnection for Electronics and Sensors – Past, Present and Future", Circuit World, Vol. 36 No. 3. https://doi.org/10.1108/cw.2010.21736cac.002

Packaging and Interconnection for Electronics and Sensors – Past, Present and Future

Article Type: Conferences and exhibitions From: Circuit World, Volume 36, Issue 3

A Seminar to Mark the Retirement of David Pedder, TWI, Granta Park, Cambridge, UK, February 10, 2010.

On February 10, 2010, TWI hosted a one-day seminar entitled “Packaging and Interconnection for Electronics and Sensors – Past, Present and Future”. This was a special event that had been organised to mark the retirement of Dr David Pedder, who had been a key figure in the electronics industry since 1971. Not surprisingly, the event had proved to extremely popular and it was attended by a capacity audience of around 100 delegates. The event had been cosponsored by TWI, NMI, eKTN, and the Innovative Electronics Manufacturing Research Centre (IeMRC) and there were also a number of table top and poster exhibits.

The seminar began with Dr Pedder being called to the front of the auditorium while a review of his career was presented to the delegates by Roger Wise of TWI and his former Caswell colleague, Martin Goosey. The technical part of the day then began with a presentation entitled “Packaging of pyroelectric arrays for people counting and thermal imaging applications” by Jon Hall of Irisys. Detectors using pyroelectric arrays were finding widespread use for thermal sensing to detect and track people in supermarkets and shopping centres. The devices used in these applications operated in the 8-14 μm range and were typically based on a 16×16 array of sensor elements. The assembled devices used a sequential readout to provide data, which was processed by an ASIC. The pyroelectric ceramic used in the detector could operate at up to 150°C and it was flip chipped onto the ASIC using an isotropic conductive adhesive printed onto the diced silicon wafer. The assembly was then packaged in a low-cost 28 pin DIL based on FR4 with soldered leads. The package was fitted with a silicon window which was epoxy sealed. Although this was not a fully hermetic package tested devices still worked after one year’s exposure at 65°C and 85 per cent RH. Work was underway to shrink the pitch from 500 to 170 μm and the bump diameter from 200 to 85 μm. The ceramic thickness was also being reduced from 200 to 100 μm. The requirements for improved adhesives and stencil technology were also discussed. The alignment process using a semi-automatic bonder was also described; this was said to be capable of an accuracy of 12 μm and work to improve this was also detailed. A camera was demonstrated that combined a visible and a thermal image; this was used to spot problems in electrical and mechanical equipment. Future devices would have more bumps per wafer, possibly as many as 1 million.

The second paper of the day was given by Peter Robinson of Cambridge silicon radio (CSR) and he began by describing the wafer level chip scale package (WLCSP), which was the package of choice for handset applications. CSR had shipped around 800 million units to date and these typically had pitches of 0.5 and 0.4 mm and a moisture sensitivity level of 1. The structure of the WLCSP was detailed and these used SnAgCu solder balls. There was an ultrathin version with thinned silicon which was only ∼300 μm in total thickness. An even thinner version of 120 μm total thickness was under development. Examples of modules incorporating the device were shown, including one, where the module had been buried in a multilayer PCB. Typical problems encountered at this level included electrical and magnetic coupling between ICs and the packages. More and more modelling was being undertaken in order to minimise and, if possible, eliminate these effects. Examples of this modelling were shown which illustrated some of these interactions and included the results of dynamic IR drop analyses. There were also thermal interactions, particularly as ICs became smaller and feature integration increased. Examples of thermal interactions between the chip and package were also shown and these illustrated examples of localised heating. The example was given of switching on a Bluetooth device and how this resulted in various heat interactions across the device. Other examples shown highlighted some of the mechanical problems that could be encountered when moving to the use of low-K dielectrics. Peter concluded by showing results illustrating how a newly developed assembly process gave enhanced drop test performance. Current work at CSR was focussing on the use of low-K dielectrics, copper wire bonding, and WLCSP processing and reliability.

David Selviah of University College, London, then gave a presentation entitled “Polymer wave guide optical interconnect manufacturing” in which he described a large multipartner project that had been funded by the IeMRC. David began by comparing copper tracks with optical waveguides for high-bit rate interconnections. Copper tracks suffered from EMI, crosstalk, loss, and required impedance control in order to minimise back reflection. They also required more expensive board materials. Optical waveguides offered low-loss, low-crosstalk, low-power consumption, and reduced cost, but they could not transmit electrical power. The focus of the project had been on multimode waveguides operating at 10 Gb/s that were incorporated onto a 19-inch PCB. The project included eight industrial partners and three universities. Waveguide materials had been supplied by Dow Corning and Excellis and assistance with the PCB design rules and tools had been provided by Cadence. End-users who were interested in implementing the technology were Renishaw, Xyratex, and BAe Systems. A direct laser writing process had been used to cure the waveguide polymer and, using this approach, it was possible to produce sharply defined features via modification of the beam profile. It was also possible to overlap waveguides. A laser ablation technique had also been developed as an alternative method for forming waveguides and this had been demonstrated using excimer, carbon dioxide, and UV Nd:YAG lasers. With the CO₂ laser the ablation process was mainly thermal, whereas with the Nd:YAG laser it was a photochemically dominated process. Work had also been carried out to develop an inkjet process for depositing waveguides. This offered a low-cost, low-waste route with controlled selective deposition of both core and cladding materials. For this process, the wettability of the substrate was critical to the subsequent quality of the waveguide. A demonstrator device was described and this had been built at Stevenage Circuits with the waveguides being added by IBM in Zurich.

The final presentation in the morning session was given by Eric Beyne of IMEC in Leuven, Belgium and he spoke on “MEMS packaging and 3D interconnection”. Eric began be highlighting that MEMS packaging was particularly important because of the fragile moving parts that they typically contained such as gyroscopes, motors, cantilevers, etc. He then described work-linked to an EU-funded project called MEMSPACK which was running until May 2011. Eric described the basic process for making MEMS and sensor devices. Encapsulation was typically carried out at the wafer level and needed to be hermetic. The various possible wafer level package types were then described. Through silicon vias could provide an important route for providing the escape I/Os for such devices and could be followed by flip-chip bumping. Sealing methods were also described and these included the use of polymer seals, although these did not provide a true hermetic seal. Metal seals could be hermetic but required the processing of metal structures on the silicon substrate. Data were provided showing helium leak rates with BCB polymer seals. Solder seals could also be used to give good leakage rates and the importance of the seal dimensions was highlighted. Many different metal alloys could be used in the transient liquid phase bonding process. IMEC used copper-tin, which had a process time and temperature of four minutes and 260°C, respectively; the remelt temperature was >415°C. Control of the process parameters was critical if the sealing process was to be successful, cracking was to be avoided and the joints were to be leak tight. Eric then described a novel technique for metal-to-metal bonding which used a high-precision diamond bit to cut bumps on the fly. This technique enabled the copper-to-copper bonding temperature to be reduced from >300 to ∼225°C. The technique could also be used with copper and tin. The presentation concluded with a description of the through silicon via process.

Following a networking lunch, the first presentation of the afternoon was given by Martin Goosey, Industrial Director of the IeMRC. The presentation was entitled “Advanced PCB interconnection technology – materials challenges” and, after a brief introduction to the work of the IeMRC, Martin discussed some of the materials related challenges related to the manufacture of high-performance circuit boards. Martin began by describing how PCBs continued to be the interconnection medium for most electronics and highlighted how their materials and manufacturing processes had evolved to meet the evolving performance demands of end-users. He then went on to discuss three examples of where improved performance was required from PCB substrates and how, by changing the basic chemistry, it was possible to offer the required enhancements. The examples cited were the need for higher thermal stability, the move to halogen-free, and the requirement for better performance in higher frequency applications. Martin described how moving away from the basic chemistry of FR4 with its dicyandiamide curing system to the use of novolac resin systems could give better thermal stability. He also highlighted how changes in the basic chemistry of the resin systems of PCB substrates could also lead to a need to adjust the chemical processing stages such as desmear. Other ways of offering these enhancements were also described and it was noted that higher performance substrates were often more expensive than their conventional standard counterparts.

Cian O’Mathuna of the Tyndall Institute in Cork then gave a presentation on “Magnetics on silicon – an enabling technology platform for power supply on chip” Cian began by giving an introduction to the Tyndall Institute which now employed over 400 people. One key area of activity was on autonomous sensors and their interfaces to the outside physical world. These often needed to be self-powered, networked, and with a wireless communications capability in order that they could be used in “deploy and forget” applications. Ideally, they should also be very low-cost and occupy little space. Current work was focussing on applications in the energy, environmental, and health sectors. An example was shown of a PCB embedded magnetic flux gate sensor. The vision for a power supply on a chip was described and the likely power requirements described. An example was also detailed in which the accompanying leadframe could provide the function of an inductor. A bottleneck was the integration of passives onto the silicon and the key to achieving this was having a silicon compatible device footprint. NXP were cited as having developed trench capacitors on silicon. Micro-fabricated magnetics had been put on silicon via electroplated windings and this was said to be a low-cost process.

The third presentation of the afternoon session was entitled “Everything including the chip: DfM challenges and advanced packaging technologies” and was given by Jonathan Edwards of ST-Ericsson. Jonathan began by describing how the level of functionality and miniaturisation required by today’s mobile wireless devices required a level of integration that could not be achieved by Moore’s Law scaling alone. Advanced packaging solutions were needed to increase the effective device packaging density. He then went on to show how the packaging roadmap had evolved over the past decade in order to meet the needs of mobile wireless applications, moving from the simple single die wire bonded BGA to today’s complex variety of package solutions, which included flip-chip wafer level chip scale packages, multi-die modules, chip stacking, and multichip system in package on wafer. He then presented details of the embedded wafer level ball grid array technology developed jointly by ST, Infineon, and STATSChipPAC.

There then followed a paper from Zarlink on medical device packaging and this was given jointly by Piers Tremlett and Henry Higgins. The presentation was called “Medical electronics and miniaturisation: a fantastic voyage”. The presentation began with an historic look at some of the crude techniques that had been used in the past for examining the body, up to the employment of the present day endoscope. The basic structure of a camera pill was then outlined and this was described as effectively being a miniature submarine that moved by electro-stimulation of the bowel of oesophageal muscles. Examples of prototypes of these capsules were shown, along with the electronics they incorporated. The electronics employed bare die chip and wire, flip chip, die stacking, integrated passives, and a range of other advanced technologies. These devices enabled pictures to be taken of areas that had never before been seen, with little inconvenience to the patient. The evolution of the pace maker was then described and the example was given of one man who lived to the age of 86 years having had 26 pacemakers fitted over a period of 43 years. Zarlink had contributed to pacemaker development with their remote monitoring “broadband for the heart” technology. This utilised RF SiP packaging technology and the use of die embedded in the PCB. The presentation concluded with a review of some of the related projects in which Zarlink were involved and these included NEMO, SIMM, and TIPS.

Quite appropriately, the last paper of the day was given by David Pedder and was entitled “Passive integration and system in package: past present and future”. David began by discussing some of the projects he had worked on over the last four decades, beginning with his research in the 1970s on internally oxidised alloy powders and then moving on to his early involvement in surface mount technology during the 1980s. This work involved thermal cycling reliability testing of ceramic packages on FR4, FR4-Cu-Invar, and other materials. He also described his 1980s work on uncooled IR sensors, which involved flip-chip attachment of the pyroelectric sensor arrays onto silicon. At this time, he also worked on silicon-on-silicon MCM and flip-chip GaAs MMICs. During the 1990s, there was work on MCMs for RF applications and many other interconnect- and packaging-related projects. For the first decade of the new century David chose, as examples of his work, the ADEPT project and the EPPIC faraday partnership, which had the objective of “Consolidating the packaging and interconnection capabilities of the electronics and photonics sector”. He then went on to discuss system in package (SiP) and the various categories and architectures. There was also a discussion of the capabilities of the different types of integrated passives. For this decade, David covered precision passives for micro-module (PPM2) applications and highlighted SIC-based SiP technology, along with the further development of high-density interconnects, active and passive substrates, and a number of example demonstrators and applications.

The seminar was brought to a close by Roger Wise of TWI, who observed that the meeting had drawn out a number of themes for future development including three-dimensional packaging and integration and integrated passives. Future challenges were likely to occur in the medical electronics area where further miniaturisation and reliability were considered to be possible topics for collaborative projects. The event concluded with a champagne reception hosted by David Pedder.

Martin Goosey