iMAPS – Basic Packaging Workshop, 4 December 2008, Unisem Europe Ltd, Croespenmaen, Newport

Circuit World

ISSN: 0305-6120

Article publication date: 15 May 2009



Goosey, M. (2009), "iMAPS – Basic Packaging Workshop, 4 December 2008, Unisem Europe Ltd, Croespenmaen, Newport", Circuit World, Vol. 35 No. 2.



Emerald Group Publishing Limited

Copyright © 2009, Emerald Group Publishing Limited

iMAPS – Basic Packaging Workshop, 4 December 2008, Unisem Europe Ltd, Croespenmaen, Newport

Article Type: Conferences and exhibitions From: Circuit World, Volume 35, Issue 2

On Thursday, 4 December 2008, Unisem (Europe) Ltd in Croespenmaen near Newport, South Wales, played host to an iMAPS – Basic Packaging Workshop (Figure 1).

 Figure 1 L to R; Andy Longford (iMAPS), Melvin Ilagan (Unisem), Salem
Belmeguenai (Unisem) and David Lowrie (iMAPS)

Figure 1 L to R; Andy Longford (iMAPS), Melvin Ilagan (Unisem), Salem Belmeguenai (Unisem) and David Lowrie (iMAPS)

Andy Longford, the UK Chairman of International Microelectronic Packaging Society (iMAPs), welcomed the large group of attendees to the technology workshop and Melvin Ilagan of Unisem then gave an introductory overview of Unisem, the company’s activities and its new business model. The company was moving away from being a high-volume assembly organisation to one producing lower volumes with an enhanced service and fast turnaround time capability. He outlined the challenges for European-based high-volume producers in trying to compete with similar Far East-based operations. Unisem has five facilities around the world with three in the Far East, one in Europe and one in the USA. The company offers a broad service portfolio covering assembly and test with a turnkey offering from wafer probe to final shipment. The Newport site was the only SATS provider in Europe and offers an advanced test capability for RF and mixed signal devices coupled with a lower to medium volume capability and turnaround time as fast as 8 h.

Andy Longford then gave an overview of iMAPS and its mission. iMAPS has 287 corporate members and 41 chapters globally. It was formed in 1996, when IEPS and ISHM merged and there are over 4,000 individual members with 130 based in the UK. iMAPS as also member of the UK Electronics Alliance. Andy then moved on to give a presentation on the packaging market and trends in packaging technologies. Unit IC shipments had grown by around 120 per cent over the last seven years and further compound annual growth of 9.55 per cent had been predicted for the period 2007-2012. This represented an increase in value from $151 to 261 billion. In 2007, Europe represented 16 per cent of the packaging market, with the USA at 30 per cent and the Far East having the biggest share of 54 per cent. It was predicted that, along with the predicted growth, there would also be cost increases in packaging over the same period. The key drivers impacting packaging were; time to market, ways to lower costs, the effect of package parameters, fabrication infrastructure, the International Technology Roadmap for Semiconductors (ITRS) roadmap and market pull. Andy then presented the market shares of the main package types and stated that, in 2007, the eight most popular package types accounted for 186 billion units. In Europe, the trend was moving to more advanced packaging such as that associated with MEMS, photovoltaics, opto devices, SiP and wafer-level packaging (WLP) and this was being driven by needs in automotive, broadcast, communications, medical and military applications, which were inherently low volume but high value. He then went on to state that new expertise was developing in Europe where there was also a lead in packaging equipment. Applications using through silicon vias (TSVs) were also beginning to emerge, although there were still questions over just when the vias should be made, i.e. in the wafer fab or during the later stages of the assembly process. The biggest growth to 2012 would be in the area of opto device packaging.

The second presentation of the day was given by Alan Evans of Unisem and was entitled “Package technology trends”. Alan began by giving a basic definition of packaging and outlining the key market drivers which were said to be performance, size, weight and cost. He then described the proliferation of different packaging types that were needed to meet these requirements and the evolution from leaded to leadless packaging and from single chip to multiple chip module (MCM) and SiP. An example was shown of a 10 × 10 mm land grid array package that contained four active die and 70 silicon passives. Another trend was the move from chip scale packaging (CSP) to WLP and wafer level CSP (i.e. a bumped silicon die). In wire bonding, there was an increasing interest in moving away from gold wire to copper wire in order to reduce costs, especially in packages with large numbers of wire bonds. With this proliferation of package types, it was important to make the correct package choices and as an integral part of the semiconductor design and production flow, taking into account performance requirements, die design, application and cost.

John Sweet of Loadpoint Ltd then covered “Dicing and Associated Activities”. Loadpoint is a European SME making dicing equipment and it currently has 920 machines installed worldwide. The industry is typically dicing wafers up to 300 mm in diameter but there are plans to move to 450 mm wafers. He described the various processes that could be used and how they differed. The key techniques are dicing, scribe dicing and singulation. It is important to design for dicing and to take into account the thickness of the material, street width, material sensitivity and any thinning requirements. Loadpoint are currently exploring the use of multiple dicing blades. Dicing performance is influenced by dicing speed and, typically, the best speeds are around 40 k rpm but this varied with material type. There were some new materials being found in packages, such as stainless steel in devices for medical applications. Delivery of coolant is critical, as is wafer washing with deionised water and this must be done within 45 s of completing the dicing operation. There is also a growing need to saw stacks containing a multiplicity of different materials.

Dr Mark Currie of Henkel Technologies then gave a presentation entitled “Understanding the soldering solution reliability drivers for die attach” in which he discussed the key factors influencing material choices, e.g. the need for thermal and or electrical conductivity. Currently, die attach with organic pastes accounted for more than 70 per cent of the market. However, solder offered good thermal and electrical performance but needed a special backside metallisation which typically also required a forming gas and nitrogen atmosphere. For power packages, gold/tin is being used but it is also expensive as the alloy is 80 per cent gold. Elsewhere, high-lead alloys are widely used and they are currently “RoHS” exempt. Lead-free options are also available but there is no real high-temperature lead-free solution (apart from Au/Sn). The high-lead options include, amongst others, PbSn10, PbSn10Ag2, PbSn5Ag2.5 and PbSn2Ag2.5. Other die attach materials are solder paste and solder wire but both require a forming gas reflow process. Solder pastes are available with no clean fluxes but could still require a post-die attach clean. The requirements for future pastes and wires were also described; there is a growing interest in halogen-free, no-clean solder pastes. Other requirements include excellent wetting, low-void incidence, good storage life and post-reflow cleanability. Currently, there was said to be limited published work on void levels for die attach applications, yet many factors were known to impact void formation such as solvent concentration, reflow profile and activator concentration. The performance of the flux was assessed to J. Std 004-A and there are a further number of reliability tests that are used after solder attach.

Before an excellent lunch there was an opportunity to take tour of the Unisem facility where it was possible to see the wide and comprehensive range of assembly and test equipment that could address all aspects of the processing from incoming wafer handling to final testing and shipping.

The first afternoon session began with a presentation form Hugh de Lacy of TS2 Micro Ltd who gave an overview of the wire bonding process in a talk entitled “Ins and outs of wire bonding”. Hugh began by reviewing the history of wire bonding, which was said to have first been used in the 1950s on discrete transistors. Gold thermo-compression bonding developed during the 1950s with ultrasonic aluminium bonding starting in the mid-1960s. The different techniques were then described and compared. Gold wire bonding is faster than aluminium or gold wedge bonding and is also compatible with the widely used transfer moulding encapsulation technique. However, wedge bonding achieves finer pitch than ball bonding (25 versus 40 μm). Also, ball bonding is not compatible with larger wire diameters (>100 μm), whereas aluminium is; it is also cheaper. In the past, there had been suggestions that tape automated bonding would eventually replace wire bonding but this has not yet happened due to the major performance enhancements in wire bonding equipment. Each technique has key application areas; gold ball bonding is used for high-volume plastic encapsulated devices, whereas aluminium wedge bonding is typically used with high-reliability, high-temperature and high-power devices. Gold wedge bonding is increasingly used in microwave device applications. The elemental composition of the wires is a key factor in determining the performance of the bonds. Although the metals used are typically very pure, small additions of other elements are made to improve properties such as tensile strength and loop control. Aluminium often has an addition of 1.0 per cent silicon or 0.5-1.0 per cent of magnesium to improve the drawing process. However, for larger diameter wirers pure aluminium could be used. Copper is also being used to replace gold in some applications. Wire bondable finishes were then described. On PCBs, nickel-gold is the most popular finish but nickel/gold/palladium is an attractive alternative allowing less gold to be deposited (>0.1 μm). With lead frames, gold, silver and nickel/palladium finishes are popular. MIL Standard 883 is still used to define the wire pull test and both pull and shear testing is popular. Common problems were then described and these include cratering of bond pads, non-welding of bonds and intermetallic growth (e.g. Au/Al and Kirkendall voiding). Currently, the key developments are taking place around fine pitch bonding (<40 μm pitch and 50 μm loop height) and with gold stud bumping for flip chip applications. Gold stud bumping is cost effective at low volumes. Copper ball bonding onto aluminium bond pads offers savings with high-lead count devices and it is better than gold in respect of intermetallic formation. Flip chip is becoming increasingly popular, especially for very high-pad count applications.

The next presentation was on “Flip Chip Technology” and it was presented by Helen Goddin of TWI who began by defining flip chip and comparing the evolution of different processes. Flip chip offers the potential for size reductions and enhanced performance but is more difficult to inspect and to rework. The under bump metallisation could be deposited by a number of techniques such as etching or via a mask process and the bumps could also be formed in four different ways namely stud bumping, plating of gold bumps, using silver filled epoxy and solder bumping. With solder bumping there are also a number of methods that could be used to deposit the solder and these include stencil printing, evaporation (as used in the lead-free solder bump manufacturing C4 process), plating through resist defined holes and by direct attachment of solder balls. The solder balls are typically made of a 95 per cent Pb alloy with a melting point of around 300°C. Bonding could be achieved by thermocompression bonding, thermosonic bonding or adhesive bonding (isotropic conductive adhesives, anisotropic conductive adhesives (ACAs) and non-conducting). When using underfills it is important to choose the appropriate material in terms of properties such as Young’s modulus and Tg. There are a wide range of current applications for flip chip and in the future the technique would increasingly find use in SiP applications, as well as in smart tags and sensor and automotive applications.

Steven Clark of Dage then described “Bond Testing Applications and Equipment” and he began by covering bond testing applications and why testing was needed. It is used for testing the strength of interconnects in both a destructive and non-destructive manner; each is covered by standards. The main applications are in ball shear, wire pull, die shear and in hot and cold bump pull testing. Ball shear testing is a direct test of the first bond and is also sometimes useful when wire pull testing is not possible. Steve discussed the applicable industry standards and the potential issues caused by the move to lead-free assembly. There is a need to study brittle fracture failure and his company has developed a high-speed bond tester. This applies a high-shear rate, e.g. 0.1 to 2.0 m/s, and a pull rate of 5.0-400 mm/s. This is intended to simulate what would happen in real life loading and drop testing and it has been found that the test equipment needs to employ high-bandwidth transducers. Failure modes versus shear testing speeds have also been studied and it is a technique that could be used for material screening and process control applications.

The final presentation of the day was given by Iain Gardner of Wafer Data Ltd and was on the subject of IC testing. Iain described the different testing processes for wafers. After the wafer fabrication process, testing is performed on the drop in die or on the test structures in the scribe lines. Probe testing is done before and after assembly and thus, if performed at the appropriate time, packaging costs could be avoided by pre-screening. There is a variety of probe test equipment manufacturers but the number has actually been contracting in recent years. Test equipment models are usually targeted at specific products as each device needs its own test programme. However, there is a move towards the use of Standard Test Data Format, which uses an open standard from Teradyne. There are various probe card types roughly falling into two categories and these are known as vertical and cantilever probe cards. Probe cards could be expensive to build and service, so they should be inspected regularly and extra care should be taken with bumped wafers. There has been a move to inkless testing and this offers additional benefits before the die is assembled.

The workshop was brought to a close by Andy Longford, who thanked the speakers for their efforts and Unisem for hosting the event. The large audience clearly confirmed that there was a real need for this type of event and iMAPs are to be congratulated for organising what turned out to be such a valuable educational and networking event.

Martin GooseyDecember 2008

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