Assembly in electronic manufacturing: chances and challenges

Citation

Xiong, Z. (2010), "Assembly in electronic manufacturing: chances and challenges", Assembly Automation, Vol. 30 No. 4. https://doi.org/10.1108/aa.2010.03330daa.002

Assembly in electronic manufacturing: chances and challenges

Article Type: Viewpoint From: Assembly Automation, Volume 30, Issue 4

Recently, the electronic industry has become the biggest industry and one of the most dynamic fields in the world. One major driving force relies on the rapid development of electronic manufacturing technologies, from the front-end to the back-end, including semiconductor fabrication, electronic packaging and assembly. Among them, assembly technology is playing an important role in many aspects, and will meet more research chances and development challenges in the near future.

In the past several decades, continuous complementary metal-oxide semiconductor (CMOS) scaling at the Moore’s Law rate maintained the continuous growth of the industry. Those high end fabrication processes have few connections with what we know as assembly technology. When we talk about electronic assembly, we may easily think about the well developed through hole technology and surface mount technology. From day-to-day, thousands and thousands printed circuit boards and electronic products are made by both electronic and mechanical assembly lines. Despite of the big market size and various automated equipments, electronic assembly is classified as low end technology. Compared with electronic assembly, electronic packaging makes chips from bare dies, and demands much higher precision assembly technology. The dominating Wire Bonding and the developing Flip Chip technologies continuously find their ways to meet the market requirement. Unfortunately, we find limited new research on assembly technology in the above fields, owing to the abundant equipment suppliers in the market.

However, the industry is rapidly approaching the limits of traditional CMOS scaling. Assembly and packaging is now a limiting factor in both cost and performance for electronic systems. According to International Technology Roadmap for Semiconductors (ITRS, 2009), compared with traditional in plane integration, an era of 3D integration is coming, in which Wafer Level Packaging and vertical system integration are two distinct features. The direct benefits of 3D integration include improvement of integration density and reduction of interconnection length. With the continuous increase of wafer size from 200 to 300 mm, and to 450 mm in the future, while the diameters of bumps and pads on the wafer are continuously shrinking from 100 to 80 μm, and to 40 μm further, it is extremely challenging to assemble two such wafers together precisely and stably. For 3D integration utilizing through silicon via, the diameter of the vias may go down to several microns, which makes the die-to-die or die-to-wafer integration very challenging. More challenges for assembly technology are listed below (Garrou et al., 2008):

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  handling and manipulation of thinned wafer/die, whose thickness is 50-75 μm now and will be several microns;

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  stacking of multiple dies, up to eight-ten layers;

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  high precision alignment with accuracy down to sub-micro;

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  assembly force sensing and control; and

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  high assembly throughput.

These challenges impose significant investment and R&D pressure on current assembly and packaging suppliers. Meanwhile, the fact also gives great opportunities to academic and industrial communities. It is noticed that recently there has been increase in cooperative development represented by university programs and research consortia (ITRS, 2009). The acceleration of investment and the efficient coordination of research will further stimulate the development of assembly and packaging technology, and continuously maintain the progress in cost reduction and performance improvement for electronic systems.

Zhenhua XiongBased at State Key Laboratory of Mechanical System and Vibration, School of Mechanical Engineering, Shanghai Jiao Tong University, Shanghai, People’s Republic of China