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Tag cache memory
Tag cache memory
Keywords: Data, Microprocessors
Applicant: Motorola Inc. (US)Patent number: US5920890Publication date: 6 July 1999
Title: Distributed tag cache memory system and method for storing data in the same
Low power design has been gaining importance in microprocessor design owing to widespread use of portable and handheld applications. Many portable and embedded microprocessors consume a significant amount of energy for accessing memory. Power consumed by instruction references, in a typical microprocessor, is much higher than the power consumed by data references. Thus reducing instruction fetch energy can be beneficial in such applications. The invention refers to a loop cache, which is used in a data processing system for supplying instructions to a CPU to avoid accessing a main memory. Whether instructions stored in the loop cache can be supplied to the CPU is determined by a distributed tag associated with the instruction address computed by the CPU. The instruction address includes an LCACHE index portion, an ITAG portion and a GTAG. The LCACHE index selects corresponding locations in each of an ITAG array, an instruction array, and a valid bit array. A stored GTAG value is chosen irrespective of where LCACHE index is pointing. The GTAG portion of the instruction address is compared with the stored GTAG value. The ITAG portion of instruction address is compared with the indexed ITAG of the ITAG array. If both the GTAG and ITAG compare favourably, the instruction is supplied from the loop cache to the CPU, rather than from the memory.