The Purpose of this research is to make an energy efficient finite state machine (FSM) in order to achieve the core objective of green computing because FSM is an indispensable part of multiple computer hardware.
This study uses ultra-scale plus FPGA architecture in place of seven-series field-programmable gate array (FPGA) for the implementation of the FSM design and also uses output load scaling for the design of environment-friendly FSM. This design study is done using Verilog Hardware description language and Vivado integrated system environment design tools and implemented on 16 nm ultra-scale FPGA architecture.
There is up to 98.57% reduction in dynamic power when operating frequency is managed as per smart job scheduling. There is up to a 21.97% reduction in static power with proper management of output load capacitance. There is up to 98.43% saving in dynamic power with the proposed management of output load capacitance.
The proposed design will be environment friendly that eventually leads to the green earth. This is the main motive of the research area i.e. green computing.
This research work was supported by Gyancity Research Consultancy Pvt. Ltd. (Grant No 3/2019).
Pandey, B., Tomar, G.S., Bhadoria, R.S., Hussain, D.M.A. and Rodriguez Rodriguez, C. (2021), "Environment-friendly FSM design on ultra-scale architecture: energy-efficient green computing approach", World Journal of Engineering, Vol. 18 No. 4, pp. 553-557. https://doi.org/10.1108/WJE-08-2020-0397
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