TY  - JOUR
AB  - Purpose This study aims to propose a modified topology for an asymmetric multilevel inverter as a basic module that generates 13-level output voltage waveform. The basic module consists of eight switches (unidirectional and bidirectional switch) and four DC voltage sources with unequal magnitudes. The proposed topology reduces the number of switches, isolated DC sources, cost and size of the circuit significantly as compared to other topologies. In addition, the proposed circuit provides a modular structure for a multilevel inverter.Design/methodology/approach The proposed configuration is implemented through simulation and hardware development of a single-phase 13-level inverter prototype. A multicarrier-based pulse width modulation scheme is adopted for generating switching signals by using dSPACE real-time controller.Findings To demonstrate the advantages of the proposed configuration, a comparative analysis is carried out with other multilevel topologies in terms of number of switches, gate driver circuits, on-state switches and blocking voltage on the switches. The comparison results confirmed that the proposed configuration requires less number of components for the same number of voltage levels. Moreover, the peak inverse voltage on switches and losses is lower in the proposed configuration.Originality/value In the available literature, numerous topologies are presented with main emphasis on the reduced components count. In this study, the authors proposed a new topology for an asymmetrical source configuration. The performance of the proposed topology under steady-state and dynamic conditions is evaluated using simulation and experimental implementation.
VL  - 16
IS  - 1
SN  - 1708-5284
DO  - 10.1108/WJE-01-2017-0010
UR  - https://doi.org/10.1108/WJE-01-2017-0010
AU  - Mohanty Kanungo Barada
AU  - Thakre Kishor
AU  - Chatterjee Aditi
AU  - Nayak Ashwini Kumar
AU  - Kommukuri Vinaya Sagar
PY  - 2019
Y1  - 2019/01/01
TI  - Reduction in components using modified topology for asymmetrical multilevel inverter
T2  - World Journal of Engineering
PB  - Emerald Publishing Limited
SP  - 71
EP  - 77
Y2  - 2024/04/24
ER  -