Failure analysis of solder layer in power transistor
Soldering & Surface Mount Technology
ISSN: 0954-0911
Article publication date: 19 December 2017
Issue publication date: 23 January 2018
Abstract
Purpose
The purpose of this paper is to present a failure analysis of the solder layer in a Darlington power transistor in a TO-3 package.
Design/methodology/approach
A failed Darlington power transistor in a TO-3 package was examined by different kinds of failure analysis techniques. At first, internal gas analysis was conducted to measure the atmosphere. Then, scanning acoustic microscopy (SAM) was performed to check the quality of the solder layers in the failed device, and the failure location was determined in the solder layer between chip and substrate. Next, the failed device was decapped to observe the defects. After removing the chip from the substrate, energy dispersive spectroscopy (EDS) and X-ray photoelectron spectroscopy (XPS) were applied and the main elemental composition of the solder layer was identified.
Findings
Internal gas analysis indicated that the moisture and oxygen contents exceeded the allowed maximum value. Large areas of voids were found in the solder layer by SAM. The main elemental compositions of the solder layer were identified by scanning electron microscopy and EDS. Furthermore, the valences of the chemical components in the solder layer were identified by XPS. Except for the few simple substances of the initial solder material, the chemical formulae of oxidation products in the solder layer were deduced. In addition, the root causes are also discussed.
Originality/value
This paper focuses on the solder layer failure of a power transistor. Factors such as the presence of oxygen, voids and other factors, which can cause transistor damage, were comprehensively analyzed. The analysis process is worth learning from and the results can be used to improve the reliability of power devices in this kind of package.
Keywords
Acknowledgements
The research in this article is supported by the Fund of China (Grant No: 61400020105).
Citation
Jiang, M., Fu, G., Wan, B., Xue, P., Qiu, Y. and Li, Y. (2020), "Failure analysis of solder layer in power transistor", Soldering & Surface Mount Technology, Vol. 30 No. 1, pp. 49-56. https://doi.org/10.1108/SSMT-07-2017-0019
Publisher
:Emerald Publishing Limited
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