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Advancing packaging technology: computational fluid dynamics modeling for capillary underfill encapsulant in multi-chip heterogenous packages

Muhammad Aqil Azman (School of Mechanical Engineering, Universiti Sains Malaysia – Kampus Kejuruteraan, Nibong Tebal, Malaysia and Department of Assembly and Test Technology Development, Intel Microelectronics, Kulim, Malaysia)
Mz Abdullah (School of Mechanical Engineering, Universiti Sains Malaysia – Engineering Campus Seri Ampangan, Nibong Tebal, Malaysia)
Wei Keat Loh (Department of Assembly and Test Technology Development, Intel Microelectronics, Kulim, Malaysia)
Chun Keang Ooi (Department of Assembly and Test Technology Development, Intel Microelectronics, Kulim, Malaysia)

Soldering & Surface Mount Technology

ISSN: 0954-0911

Article publication date: 16 October 2024

56

Abstract

Purpose

The purpose of this study is to investigate the dynamics of capillary underfill flow (CUF) in flip-chip packaging, particularly in a multi-chip configuration. The study aims to understand how various parameters, such as chip-to-chip spacing (S12), chip thickness (tc) and others, affect the underfill flow process. By using computational fluid dynamics (CFD) simulations and experimental studies, the goal is to provide insights into understanding the dynamics of CUF in heterogeneous electronic packaging.

Design/methodology/approach

The paper introduces a CFD analysis and experimental study on CUF in a multi-chip configuration, aiming to understand underfill flow dynamics. A 3D geometry models of multi-chip arrangement are created using computer-aided design (CAD) software. After that, the CAD models are meshed and simulated in Ansys Fluent using incompressible and non-Newtonian fluid properties. The study maintains S12 of 2.86 and tc of 22.29 between experimental and simulation data for results validation. Next, a various of S12 values (1.14, 2.86, 5.71, 8.57, 14.29 and 20) which focus on tc of 22.29 have been investigated. Further studies have been conduct using S12 of 5.71 and tc of 8.00, 14.29 and 22.29.

Findings

Results show a strong correlation between simulation and experiment which validate the correctness and robustness of simulation. Further parameter’s studies using simulation for various of S12 indicated that higher S12 values lead to faster flow. This effect is due to large underfill weight from reservoir able to flow into S12 region which contributed to higher mass momentum movement. Furthermore, the effect of various of tc shows that the thicker the chip the faster the underfill to flow in S12 region.

Research limitations/implications

The intentional exclusion of solder bump pattern arrangements from the experiment and simulation may limit the study's ability to fully understand the impact of solder bump patterns on underfill flow. Therefore, more parameters can be investigated such as solder bump pattern, underfill weight and dispense pattern in the future using CFD.

Practical implications

The manuscript provides a comprehensive examination of the contributions of CFD to the advancement of knowledge regarding CUF phenomena in heterogeneous electronic packaging assemblies. Moreover, it delineates the utilization of CFD methodologies to assess the influence of chip-to-chip spacing (S12) and the thickness of the chip (tc) on the underfill flow characteristics.

Originality/value

This paper fulfills an identified need of computational fluid dynamics method to study capillary underfill flow dynamics in heterogenous electronic packaging.

Keywords

Acknowledgements

The authors would like to greatly acknowledge Intel for funding this research. Intel’s engineer, Ooi Renn Chan, Li Wei, Edvin Cetegen, Leow Yen Houng and Omar Ali for supporting documents and sharing knowledge. Finally special thanks to Universiti Sains Malaysia engineering faculty management for their trust, support and encouragement.

Citation

Azman, M.A., Abdullah, M., Loh, W.K. and Ooi, C.K. (2024), "Advancing packaging technology: computational fluid dynamics modeling for capillary underfill encapsulant in multi-chip heterogenous packages", Soldering & Surface Mount Technology, Vol. ahead-of-print No. ahead-of-print. https://doi.org/10.1108/SSMT-05-2024-0022

Publisher

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Emerald Publishing Limited

Copyright © 2024, Emerald Publishing Limited

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