To read this content please select one of the options below:

Packaging design and thermal analysis for 1 mm2 high power VCSEL

Khairul Mohd Arshad (Institute of Nano Optoelectronics Research and Technology (INOR), Universiti Sains Malaysia, Sains@USM, Bayan Lepas, Pulau Pinang, Malaysia)
Muhamad Mat Noor (Faculty of Mechanical and Automotive Engineering Technology, Universiti Malaysia Pahang, Pekan, Pahang, Malaysia)
Asrulnizam Abd Manaf (Collaborative Microelectronic Design Excellence Center (CEDEC), Universiti Sains Malaysia, Sains@USM, Bayan Lepas, Pulau Pinang, Malaysia)
Kawarada H. (Faculty of Science and Engineering, Waseda University, Tokyo, Japan and The Kagami Memorial Laboratory for Materials Science and Technology, Waseda University, Nishiwaseda, Shinjuku, Tokyo, Japan)
Falina S. (Collaborative Microelectronic Design Excellence Center (CEDEC), Universiti Sains Malaysia, Sains@USM, Bayan Lepas, Pulau Pinang, Malaysia)
Syamsul M. (Institute of Nano Optoelectronics Research and Technology (INOR), Universiti Sains Malaysia, Sains@USM, Bayan Lepas, Pulau Pinang, Malaysia and Faculty of Science and Engineering, Waseda University, Tokyo, Japan)

Microelectronics International

ISSN: 1356-5362

Article publication date: 15 July 2022

Issue publication date: 2 January 2023

57

Abstract

Purpose

Vertical-cavity surface-emitting laser (VCSEL) is a high-performance semiconductor device made of unique epitaxial layers grown on n-type GaAs or InP substrates. The VCSEL’s thermal resistance, Rth, is an essential metric that reflects its thermal properties and dependability. The purpose of this paper is to develop packaging for 1 mm2 VCSEL chips made of a variety of materials, such as ceramic, lead frame and printed circuit board (PCB)-based packaging, as well as provide an idea or design that can withstand and perform well in terms of Rth and heat dissipation during operation. SolidWorks 2017 and AutoCAD Mechanical 2017 software were used to publish all thoughts and ideas, including the size dimensions (x, y and z) and material choices for each package.

Design/methodology/approach

Following the modelling and material selection, the next step is to use the Ansys Mechanical Structural FEA Analysis software to simulate all packaging for Rth and determine which packaging produced the best result, therefore, determining the heat dissipation for each packing. All parameters were used based on the standard cleanroom requirement for the industrial manufacturing backend process, where the cleanroom classification is 10,000 particles (ISO 7). The results demonstrated that the ceramic and lead frame provided good Rth values of 7.3 and 7.0 K/W, respectively, when compared to the PCB, which provided more than 80 K/W; thus, the heat dissipation for PCB packaging also increased.

Findings

As a result of the research, it was determined that ceramic and lead frame packaging are appropriate and capable of delivering good Rth and heat dissipation values when compared to PCB. In comparison to PCB, which requires numerous modifications, such as adding via holes and a thermal bar in an attempt to lower the Rth value, neither packaging requires improvement. Ceramic was chosen for development based on Rth's highest performance, with the actual device consisting of a lead frame and PCB. The Zth measurement test was carried out on a ceramic package, and the Rth result was comparable to the simulation result of 7.6 K/W, indicating that simulation was already proved for research and development.

Originality/value

The purpose of this study is to determine which proposed packaging design would give the highest Rth performance of a 1 mm2 chip as well as the best heat dissipation. In comparison to other studies, VCSEL packaging used the header and window cap as package components with a wavelength of 850 nm, and other VCSEL packaging developments used the sub mount on ceramic package with an output power ranging from 500 mW to 2 W, whereas this study used a huge wavelength and an output power of 4 W.

Keywords

Acknowledgements

This research was funded by USM’s Short Term Grant, grant number “304/CINOR/6315371”. The author would like to express his gratitude to INOR, USM and FTKMA, UMP for providing research facilities

Citation

Mohd Arshad, K., Mat Noor, M., Manaf, A.A., H., K., S., F. and M., S. (2023), "Packaging design and thermal analysis for 1 mm2 high power VCSEL", Microelectronics International, Vol. 40 No. 1, pp. 26-34. https://doi.org/10.1108/MI-03-2022-0048

Publisher

:

Emerald Publishing Limited

Copyright © 2022, Emerald Publishing Limited

Related articles