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Optimization of 1-µm gate length InGaAs-InAlAs pHEMT

Naeemul Islam (School of Electrical and Electronic Engineering, Universiti Sains Malaysia – Engineering Campus Seri Ampangan, Seberang Perai Selatan, Penang, Malaysia)
Nur Syahadah Yusof (School of Electrical and Electronic Engineering, Universiti Sains Malaysia – Engineering Campus Seri Ampangan, Seberang Perai Selatan, Penang, Malaysia)
Mohamed Fauzi Packeer Mohamed (School of Electrical and Electronic Engineering, Universiti Sains Malaysia – Engineering Campus Seri Ampangan, Seberang Perai Selatan, Penang, Malaysia)
Syamsul M. (Institute of Nano Optoelectronics Research and Technology (INOR), Universiti Sains Malaysia, Penang, Malaysia)
Muhammad Firdaus Akbar Jalaludin Khan (School of Electrical and Electronic Engineering, Universiti Sains Malaysia – Engineering Campus Seri Ampangan, Seberang Perai Selatan, Penang, Malaysia)
Nor Azlin Ghazali (School of Electrical and Electronic Engineering, Universiti Sains Malaysia – Engineering Campus Seri Ampangan, Seberang Perai Selatan, Penang, Malaysia)
Mohd Hendra Hairi (Faculty of Electrical Engineering, Universiti Teknikal Malaysia Melaka, Melaka, Malaysia)

Microelectronics International

ISSN: 1356-5362

Article publication date: 11 October 2022

Issue publication date: 2 January 2023

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Abstract

Purpose

The purpose of this study is to demonstrate a pseudomorphic High Electron Mobility Transistor (pHEMT) cutoff frequency (fT) and maximum oscillation frequency (fmax) are determined by the role of its gate length (Lg). Theoretically, to obtain an Lg of 1 µm, the gate’s resist opening must be 1 µm wide. However, after the coat-expose-develop (C-E-D) process, the Lg became 13% larger after metal evaporation. This enlargement is due to both resist thickness and its profile.

Design/methodology/approach

This research aims to optimize the 1-µm Lg InGaAs-InAlAs pHEMT C-E-D process, where the diluted AZ®nLOF™ 2070 resist with AZ® EBR solvent technique has been used to solve the Lg enlargement problem. The dilution theoretically allows the changing of a resist thickness to different film thickness using the same coating parameters. Here, for getting a new resist, which is simply called AZ 0.5 µm, the experiment’s important parameters such as the coater’s spin speed of 3,000 rpm and soft bake at 110°C for 5 min are executed.

Findings

The newly mixed AZ 0.5 µm resist has presented a high resolution and undercut profile rather than standard AZ 1 µm resist. Hence, the Lg metallization after using AZ 0.5 µm optimized process showed better results than AZ 1 µm which used the standard process.

Originality/value

The outcome of the optimization has reached that it is possible to get a nearly sub-µm range gate’s opening using a diluted resist, and at the same time retaining a high resolution and undercut profile.

Keywords

Acknowledgements

This research was funded by the MINISTRY OF HIGHER EDUCATION MALAYSIA FOR FUNDAMENTALRESEARCHGRANTSCHEMEwithProjectCode: FRGS/1/2020/TK0/USM/02/30. The authors would also like to thank the Microelectronics & Nanostructures group of the School of Electrical and Electronic Engineering at The University of Manchester, UK, for the lab facilities to conduct the experiment and characterization.

Citation

Islam, N., Yusof, N.S., Packeer Mohamed, M.F., M., S., Akbar Jalaludin Khan, M.F., Ghazali, N.A. and Hairi, M.H. (2023), "Optimization of 1-µm gate length InGaAs-InAlAs pHEMT", Microelectronics International, Vol. 40 No. 1, pp. 63-67. https://doi.org/10.1108/MI-03-2022-0044

Publisher

:

Emerald Publishing Limited

Copyright © 2022, Emerald Publishing Limited

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