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The influence of a mounting manner of power MOS transistors on characteristics of the Totem-Pole circuit with RLC load

Pawel Górecki (Department of Marine Electronics, Akademia Morska w Gdyni, Gdynia, Poland)
Krzysztof Górecki (Department of Marine Electronics, Gdynia Maritime University, Gdynia, Poland)

Microelectronics International

ISSN: 1356-5362

Article publication date: 1 August 2016




The paper aims to consider the problem of the influence of mounting power metal-oxide semiconductor (MOS) transistors operating in the Totem–Pole circuit on energy losses in this circuit.


Using the computer simulation in SPICE software, the influence of such factors as on-state resistance of the channel of the MOS transistor, the self-heating phenomena in this transistor and resistance of wires connecting transistors with the other part of the circuit on characteristics of the considered circuit operating with resistor, inductor and capacitor (RLC) load is analyzed. The selected results of calculations are compared with the results of measurements.


On the basis of the obtained results of calculations, some recommendations concerning the manner of mounting the considered transistors, assuring a high value of watt-hour efficiency of the process of energy transfer to the load are formulated.

Research limitations/implications

The investigations were performed in the wide range of the frequency of the signal stimulating the considered circuit, but the results of calculations were presented for 2 selected values of this frequency only.

Practical implications

The considered analysis was performed for the circuit dedicated to power supplied of an elecrolyser.


Presented results of calculations prove that in some situations, the value of watt-hour efficiency of the considered circuit is determined by the length and the cross-section area of the applied wires bringing the signal to the connectors of the transistors and to load. On the other hand, self-heating phenomena in the power MOS transistors can lead to doubling power losses in these devices.



Górecki, P. and Górecki, K. (2016), "The influence of a mounting manner of power MOS transistors on characteristics of the Totem-Pole circuit with RLC load", Microelectronics International, Vol. 33 No. 3, pp. 176-180.



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