A fault-tolerant design for a digital comparator based on nano-scale quantum-dotcellular automata
Microelectronics International
ISSN: 1356-5362
Article publication date: 16 August 2021
Issue publication date: 27 October 2021
Abstract
Purpose
Quantum-dot Cellular Automata (QCA) is a new nano-scale transistor-less computing model. To address the scaling limitations of complementary-metal-oxide-semiconductor technology, QCA seeks to produce general computation with better results in terms of size, switching speed, energy and fault-tolerant at the nano-scale. Currently, binary information is interpreted in this technology, relying on the distribution of the arrangement of electrons in chemical molecules. Using the coplanar topology in the design of a fault-tolerant digital comparator can improve the comparator’s performance. This paper aims to present the coplanar design of a fault-tolerant digital comparator based on the majority and inverter gate in the QCA.
Design/methodology/approach
As the digital comparator is one of the essential digital circuits, in the present study, a new fault-tolerant architecture is proposed for a digital comparator based on QCA. The proposed coplanar design is realized using coplanar inverters and majority gates. The QCADesigner 2.0.3 simulator is used to simulate the suggested new fault-tolerant coplanar digital comparator.
Findings
Four elements, including cell misalignment, cell missing, extra cell and cell dislocation, are evaluated and analyzed in QCADesigner 2.0.3. The outcomes of the study demonstrate that the logical function of the built circuit is accurate. In the presence of a single missed defect, this fault-tolerant digital comparator architecture will achieve 100% fault tolerance. Also, this comparator is above 90% fault-tolerant under single-cell displacement faults and is above 95% fault-tolerant under single-cell missing defects.
Originality/value
A novel structure for the fault-tolerant digital comparator in the QCA technology was proposed used by coplanar majority and inverter. Also, the performance metrics and obtained results establish that the coplanar design can be used in the QCA circuits to produce optimized and fault-tolerant circuits.
Keywords
Acknowledgements
This paper is supported by the key project of Shaanxi Provincial Department of Education in 2021 “Study on the Discovery of Polyploid Citrus Germplasm Resources and Comprehensive Evaluation of Adversity Resistance in Southern Shaanxi”; And supported by the 2021 Shaanxi Province Philosophy and Social Sciences Major Theoretical and Practical Issues Research Project “Research on Scientific Evaluation and Innovative Utilization of Modern Architectural Heritage in the Upper and Middle Reaches of Han River”; And supported by the 2016 Soft Science Research Project of Shaanxi Provincial Department of Science and Technology titled “Research on the Livability of Immigrant Settlement Area in Southern Shaanxi Based on Post-use Evaluation” with Item Number: 2016RKM112; And supported by the 2013 Shaanxi University of Technology Ph.D. Talent Project “Hanzhong “Three-line Construction Enterprise” Industrial Heritage Protection and Utilization Strategy Research” (SLGQD13(2)-20).
Citation
Huang, W., Ren, J., Jiang, J. and Cheng, J. (2021), "A fault-tolerant design for a digital comparator based on nano-scale quantum-dotcellular automata", Microelectronics International, Vol. 38 No. 4, pp. 137-143. https://doi.org/10.1108/MI-01-2021-0006
Publisher
:Emerald Publishing Limited
Copyright © 2021, Emerald Publishing Limited