Translation rules of SysML state machine diagrams into CSP# toward formal model checking
International Journal of Web Information Systems
ISSN: 1744-0084
Article publication date: 10 June 2014
Abstract
Purpose
This study aims to describe the behavior of blocks in the system under consideration using systems modeling language (SysML) state machine diagrams. In this paper, formalization and model checking for SysML state machine diagrams have been investigated.
Design/methodology/approach
The work by Zhang and Liu (2010) proposed a formalization of SysML state machine diagrams in which the diagrams were translated into CSP# processes that could be verified by the state-of-the-art model checker PAT. In this paper, several modifications have been made and new rules have been added to the translation described in that work.
Findings
First, three translation rules were modified, which apparently are inappropriately defined according to the SysML definition of state machine diagrams. Next, we add new translation rules for two components of the diagrams – junction and choice pseudostates – which have not been dealt with previously. Further, we are implementing the automatic translation system on a web-based model-driven development tool, which reflects on our translation rules.
Originality/value
As the contribution of this work, more reasonable verification results for more general SysML state machine diagrams can be achieved.
Keywords
Acknowledgements
This research is conducted as a program for the “Regional Innovation Strategy Support Program 2012” by the Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan.
Citation
Ando, T., Yatsu, H., Kong, W., Hisazumi, K. and Fukuda, A. (2014), "Translation rules of SysML state machine diagrams into CSP# toward formal model checking", International Journal of Web Information Systems, Vol. 10 No. 2, pp. 151-169. https://doi.org/10.1108/IJWIS-02-2014-0004
Publisher
:Emerald Group Publishing Limited
Copyright © 2014, Emerald Group Publishing Limited