Edge scattering limited crosstalk analysis in adjacent multilayer graphene interconnects and its impact on gate oxide reliability

Abstract

Purpose

This paper aims to present the edge scattering dominant circuit modeling. The effect of crosstalk on gate oxide reliability (GOR), along with the mitigation using shielding technique is further studied.

Design/methodology/approach

An equivalent distributed Resistance Inductance Capacitance circuit of capacitively coupled interconnects of multilayer graphene nanoribbon (MLGNR) has been considered for T Simulation Program with Integrated Circuit Emphasis (TSPICE) simulations under functional and dynamic switching conditions. Complementary metal oxide semiconductor driver transistors are modeled by high performance predictive technology model that drive the distributed segment with a capacitive load of 0.001 fF, V_DD and clock frequency as 0.7 V and 0.2 GHz, respectively, at 14 nm technology node.

Findings

The results reveal that the crosstalk induced delay and noise area are dominated by the overall mean free path (MFP) (i.e. including the effect of edge roughness induced scattering), in contrary to, acoustic and optical scattering limited MFP with the temperature, width and length variations. Further, GOR, estimated in terms of average failure rate (AFR), shows that the shielding technique is an effective method to minimize the relative GOR failure rate by, 0.93e-7 and 0.7e-7, in comparison to the non-shielded case with variations in interconnect’s length and width, respectively.

Originality/value

Considering realistic circuit modeling for MLGNR interconnects by incorporating the edge roughness induced scattering mechanism, the outcomes exhibit more penalty in terms of crosstalk induced noise area and delay. The shielding technique is found to be an effective mitigating technique for minimizing AFR in coupled MLGNR interconnects.

Citation

Sidhu, R. and Rai, M.K. (2022), "Edge scattering limited crosstalk analysis in adjacent multilayer graphene interconnects and its impact on gate oxide reliability", Circuit World, Vol. 48 No. 4, pp. 451-463. https://doi.org/10.1108/CW-09-2020-0233