TY  - JOUR
AB  - Purpose– Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, “golden”, design of an electronic circuit. By fault simulation one simulates all situations. Normally this leads to a large list of simulations in which for each defect a steady-state (direct current (DC)) solution is determined followed by a transient simulation. The purpose of this paper is to improve the robustness and the efficiency of these simulations. Design/methodology/approach– Determining the DC solution can be very hard. For this the authors present an adaptive time-domain source stepping procedure that can deal with controlled sources. The method can easily be combined with existing pseudo-transient procedures. The method is robust and efficient. In the subsequent transient simulation the solution of a fault is compared to a golden, fault-free, solution. A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. Findings– The paper fully exploits the hierarchical structure of the circuit in the simulation process to bypass parts of the circuit that appear to be unaffected by the fault. Accurate prediction and efficient solution procedures lead to fast fault simulation. Originality/value– The fast fault simulation helps to store a database with detectable deviations for each fault. If such a detectable output “matches” a result of a product that has been returned because of malfunctioning it helps to identify the subcircuit that may contain the real fault. One aims to detect as much as possible candidate faults. Because of the many options the simulations must be very efficient.
VL  - 33
IS  - 4
SN  - 0332-1649
DO  - 10.1108/COMPEL-12-2012-0364
UR  - https://doi.org/10.1108/COMPEL-12-2012-0364
AU  - Tasic Bratislav
AU  - J. Dohmen Jos
AU  - Jan W. ter Maten E.
AU  - G.J. Beelen Theo
AU  - H.A. Schilders Wil
AU  - de Vries Alex
AU  - van Beurden Maikel
PY  - 2014
Y1  - 2014/01/01
TI  - Robust DC and efficient time-domain fast fault simulation
T2  - COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering
PB  - Emerald Group Publishing Limited
SP  - 1161
EP  - 1174
Y2  - 2024/04/18
ER  -