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GPU-based parallelization for bubble mesh generation

Van Quang Dinh (G2Elab, Grenoble, France)
Yves Marechal (G2Elab/ENSE3, Grenoble, France)



In FEM computations, the mesh quality improves the accuracy of the approximation solution and reduces the computation time. The dynamic bubble system meshing technique can provide high-quality meshes, but the packing process is time-consuming. This paper aims to improve the running time of the bubble meshing by using the advantages of parallel computing on graphics processing unit (GPU).


This paper is based on the analysis of the processing time on CPU. A massively parallel computing-based CUDA architecture is proposed to improve the bubble displacement and database updating. Constraints linked to hardware considerations are taken into account. Finally, speedup factors are provided on test cases and real scale examples.


The numerical experiences show the efficiency of parallel performance reaches a speedup of 35 compared to the serial implementation.

Research limitations/implications

This contribution is so far limited to two-dimensional (2D) geometries although the extension to three-dimension (3D) is straightforward regarding the meshing technique itself and the GPU implementation. The authors’ works are based on a CUDA environment which is widely used by developers. C\C++ and Java were the programming languages used. Other languages may of course lead to slightly different implementations.

Practical implications

This approach makes it possible to use bubble meshing technique for both initial design and optimization, as excellent meshes can be built in few seconds.


Compared to previous works, this contribution shows that the scalability of the bubble meshing technique needs to solve two key issues: reach a T(N) global cost of the implementation and reach a very fast size map interpolation strategy.



Dinh, V.Q. and Marechal, Y. (2017), "GPU-based parallelization for bubble mesh generation", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 36 No. 4, pp. 1184-1197.



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