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Circuit realization method for reduced order inductive PEEC modeling circuits

Trung-Son Nguyen ( Vietnam Fire and Rescue Police Department Hanoi Viet Nam )
Tung Le Duc ( Hanoi University of Science and Technology - School of Electrical Engineering Hanoi Viet Nam ) ( Hanoi University of Science and Technology Hanoi Viet Nam )
Son Thanh Tran ( ELECTRIC POWER UNIVERSITY Hanoi Viet Nam )
Jean-Michel Guichon ( Grenoble Electrical Engineering Laboratory Saint Martin d'heres France )
Olivier Chadebec ( CNRS Grenoble France )
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Abstract

Purpose

To synthesize equivalent circuit obtained from reduced order model of large scale inductive PEEC circuits.

Design/methodology/approach

This paper describes an original approach for reducing and synthesizing large parasitic RLM electrical circuits coming from inductive Partial Element Equivalent Circuit (PEEC) models. The proposed technique enables the re-use of the reduced order model in the time domain circuit simulation context.

Findings

The paper shows how to use a synthesis method to realize an equivalent circuit issued from compressed PEEC circuits.

Originality/value

The coupling between methods PEEC and a compressed method as Fast Multipole Method (FMM) in order to reduce time and space consuming are well-known. The innovation here is to realise a smaller circuit equivalent with the original large scale PEEC circuits to use in temporal simulation tools. Moreover, this synthesis method reduces time and memories for modelling industrial application while maintaining high accuracy.

Citation

Nguyen, T.-S., Le Duc, T., Tran, S.T., Guichon, J.-M. and Chadebec, O. (2016), "Circuit realization method for reduced order inductive PEEC modeling circuits", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 35 No. 3. https://doi.org/10.1108/COMPEL-11-2015-0425

Publisher

:

Emerald Group Publishing Limited

Copyright © 2016, Emerald Group Publishing Limited

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