Development of mathematical model and circuit emulators for four lobe memristive behaviour

Abstract

Purpose

This paper aims to develop a mathematical model for four-lobe memristor (FLM) element. The four-lobe memristive behaviour can be used in realization of hyperchaotic oscillators and implementation of multi-bit memories. For verification of the developed mathematical framework, two FLM circuit emulators have been presented using VDCC and IC LM13700, respectively.

Design/methodology/approach

A mathematical model for FLM has been developed in which, the condition for the existence of symmetrical four lobes, instances and coordinates of the end points of lobes has been derived and presented. Using this mathematical framework, a FLM emulator based on VDCC has been developed. To validate the possibility of practical implementation of FLM concept, an IC LM13700-based circuit has also been developed. The workability of VDCC based circuit has been verified by running simulations in PSPICE environment using CMOS VDCC model. Similarly, the behaviour of LM13700 IC-based circuit has been confirmed by SPICE model of LM13700 IC.

Findings

It has been shown mathematically that under certain conditions, third-order flux dependent equation of memductance can be used to generate four lobes on the transient v-i plane. Also, two FLM emulators without using any voltage multiplier circuit/IC have been reported.

Originality/value

From the best knowledge of the authors, there are no such FLM emulators that have been reported in literature so far, which operates at practical operating frequencies.

Citation

Bhardwaj, K. and Srivastava, M. (2021), "Development of mathematical model and circuit emulators for four lobe memristive behaviour", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 40 No. 1, pp. 51-61. https://doi.org/10.1108/COMPEL-06-2020-0212