Modeling gate current of nano scale MOSFET for circuit simulation

Abstract

Purpose

The purpose of this paper is to develop analytical model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET with inevitable nano scale effects (NSE).

Design/methodology/approach

A computationally efficient model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET in nano scale is presented. The model predictions are compared with the two‐dimensional Sentaurus device simulation.

Findings

Good agreement between the model and experimental data was obtained. The model also shows good agreement when compared with Sentaurus simulation and available model. It is observed that neglecting NSE may lead to large error in the calculated gate tunneling current. The findings provide a guideline to the severity of NSE from the point of view of standby power consumption. It is found that temperature and substrate bias have almost negligible effect on gate tunneling current. The gate tunneling current variation with gate bias, gate oxide thickness and source/drain overlap region have also been assessed.

Research limitations/implications

The present work is concentrated only on the gate leakage current and is useful for gate leakage analysis of the circuits.

Practical implications

The model so developed is conceptually simple, numerically efficient and can be used for circuit simulator.

Originality/value

NSE are considered while modeling the gate tunneling current through nano scale n‐channel MOSFET.

Citation

Rana, A.K., Chand, N. and Kapoor, V. (2011), "Modeling gate current of nano scale MOSFET for circuit simulation", Multidiscipline Modeling in Materials and Structures, Vol. 7 No. 2, pp. 115-130. https://doi.org/10.1108/15736101111157073