TY  - JOUR
AB  - Customer demand is driving the evolution of electronic equipment towards smaller devices with increased performance and more features. At the same time, product price should remain at a sufficiently low level with assembly process yields and throughput high. These somewhat contradictory requirements are difficult to fulfil with conventional SMD technology. Therefore, much attention is paid to packages offering small‐size and high I/O counts as well as excellent electrical properties, such as chip scale packages (CSP) and flip‐chip. CSP offers an IC in a package, which provides robustness for handling and, in some cases, decreases thermally induced stresses, and, most importantly, is SMT compatible. On the other hand, flip‐chip has the ultimate electrical performance and the smallest “package” size, with the capability of very high I/O counts. In this paper, the impacts of both CSP and flip‐chip technologies on product development and manufacturing processes is addressed.
VL  - 15
IS  - 1
SN  - 1356-5362
DO  - 10.1108/13565369810199112
UR  - https://doi.org/10.1108/13565369810199112
AU  - Savolainen Petri
PY  - 1998
Y1  - 1998/01/01
TI  - Effects of chip scale package and flip‐chip on the design and manufacturing of electronic products
T2  - Microelectronics International
PB  - MCB UP Ltd
SP  - 35
EP  - 38
Y2  - 2024/04/25
ER  -