TY  - JOUR
AB  - Purpose– The purpose of this paper is to reduce the reconfiguration time of a field‐programmable gate array (FPGA).Design/methodology/approach– The paper focuses on introducing a new temporal placement algorithm which uses a typical mathematical formalism to optimize the reconfiguration time.Findings– Results show that the algorithm decreases considerably the reconfiguration time compared with famous temporal placement algorithms.Originality/value– The paper proposes a new temporal placement algorithm which optimizes reconfiguration time of modules on the device. The studied evaluation cases show that the proposed algorithm provides very significant results in terms reconfiguration time of modules versus other well‐known algorithms used in the temporal placement field. The authors uses the eigenvalue of the Laplacian matrix.
VL  - 29
IS  - 2
SN  - 1356-5362
DO  - 10.1108/13565361211237707
UR  - https://doi.org/10.1108/13565361211237707
AU  - Ouni Bouraoui
AU  - Mtibaa Abdellatif
PY  - 2012
Y1  - 2012/01/01
TI  - Optimal placement of modules on partially reconfigurable device for reconfiguration time improvement
T2  - Microelectronics International
PB  - Emerald Group Publishing Limited
SP  - 101
EP  - 107
Y2  - 2024/04/24
ER  -