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Effects of the polarity of high‐electric field stressing on power VDMOSFETs parameters

R. El Bitar (ELIAUS, Université de Perpignan Via Domitia, Perpignan, France)
G. Salloum (Electrical Department, Roumieh, Faculty of Engineering II, Lebanese University, Beirut, Lebanon)
B. Nsouli (The Lebanese Atomic Energy Commission, CNRS, Beirut, Lebanon)

Microelectronics International

ISSN: 1356-5362

Publication date: 26 January 2010

Abstract

Purpose

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The purpose of this paper is to study the effects of positive and negative bias stressing on switching performance of power VDMOSFETs used in communication systems.

Design/methodology/approach

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A positive and a negative high‐field stress are applied on the gate oxide of MOS devices and electrical characterization is performed after each period of stress, a comparison is presented.

Findings

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Compared results between the two types of stress show that certain doses of stress can increase the device speed. The underlying changes of the threshold voltage under these two types of stress are referred to as the variation of the gate oxide‐trapped charge and interface trap densities.

Originality/value

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This paper presents new and original experiments run over a number of metal‐oxide semiconductor field effect transistor devices to compare the effects of the direction of the applied field on the degradation and the reliability of these structures.

Keywords

Citation

El Bitar, R., Salloum, G. and Nsouli, B. (2010), "Effects of the polarity of high‐electric field stressing on power VDMOSFETs parameters", Microelectronics International, Vol. 27 No. 1, pp. 17-20. https://doi.org/10.1108/13565361011009478

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Publisher

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Emerald Group Publishing Limited

Copyright © 2010, Emerald Group Publishing Limited

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