Application of a low‐glitch current cell in 10‐bit CMOS current‐steering DAC
Article publication date: 31 July 2009
The purpose of this paper is to describe the application of low‐glitch current cell in a digital to analog converter (DAC) to reduce the clock‐feedthrough effect and achieve a low power consumption.
A low‐glitch current switch cell is applied in a ten‐bit two‐stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock‐feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35μm complementary metal‐oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation.
Compared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within 0.1 LSB and the maximum power consumption is 68 mW at the sampling frequency of 100 MHz.
Comparison with other conventional work indicates that the current cell proposed in this paper shows much better performance in terms of switching spike and glitch, which may come from the extra dummy transistor in cell and reduce the clock‐feedthrough effect.
Cui, Z., Choi, J., Kim, Y., Kim, S. and Kim, N. (2009), "Application of a low‐glitch current cell in 10‐bit CMOS current‐steering DAC", Microelectronics International, Vol. 26 No. 3, pp. 35-40. https://doi.org/10.1108/13565360910981544
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