Low voltage four‐quadrant analog multiplier using dynamic threshold MOS transistors

Abstract

Purpose

Real‐time multiplication of two analog signals is one of the most important operations in analogue signal processing. Driven by low‐power and low‐voltage requirements for integrated mixedsignal portable applications, the paper's aim is to propose a novel four‐quadrant low‐voltage analog multiplier using dynamic threshold MOS transistors (DTMOS).

Design/methodology/approach

The SPICE simulations were performed with 0.25 μm technology parameters and results verify the performance of the circuit. The multiplier is simulated at low‐supply voltage of ±0.5 V.

Findings

The proposed multiplier has high linearity and simple structure hence it is suitable for high‐performance and low‐power analog VLSI applications.

Originality/value

A new low‐voltage four quadrant analog multiplier using DTMOS circuit topology is presented in the paper.

Citation

Niranjan, V. and Gupta, M. (2009), "Low voltage four‐quadrant analog multiplier using dynamic threshold MOS transistors", Microelectronics International, Vol. 26 No. 1, pp. 47-52. https://doi.org/10.1108/13565360910923179