A proposed SRAM cell for low power consumption during write operation

Abstract

Purpose

Low power static‐random access memories (SRAM) has become a critical component in modern VLSI systems. In cells, the bit‐lines are the most power consuming components because of larger power dissipation in driving long bit‐line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit‐line. The aim of the paper is to propose a new SRAM cell architecture to reduce the power consumption during write 0 and write 1 operation.

Design/methodology/approach

The proposed circuit includes two tail transistors in the pull‐down path of inv‐A and inv‐B. The simulated results of the proposed cell is compared with Conventional 6T SRAM cell and zero‐asymmetric SRAM cell.

Findings

The proposed SRAM cell consumes less power than the conventional SRAM cell during write operation. The write access delay is reported to be lower than conventional and ZA SRAMs in the proposed circuit. The read operation is similar to Conventional SRAM cell but due to tail transistors the read access delay and stability is poor in the present circuit which can be improved by careful transistors sizing.

Originality/value

The paper proposes a SRAM cell to reduce the power in write “0” as well as write “1”operation by introducing two tail transistors.

Citation

Prabhu, C.M.R. and Singh, A.K. (2009), "A proposed SRAM cell for low power consumption during write operation", Microelectronics International, Vol. 26 No. 1, pp. 37-42. https://doi.org/10.1108/13565360910923151