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Wire bond challenges in low‐k devices

Srikanth Narasimalu (Research and Development Department, ASM Technology Singapore Pte. Ltd, Singapore)

Microelectronics International

ISSN: 1356-5362

Article publication date: 1 January 2008




Ultrafine feature sizes and high‐performance requirements have necessitated the integration of low‐k dielectrics with silicon‐level interconnects. These are mechanically weaker than previous‐generation materials, a fact that has been recognized to be an industry wide issue. The inherently weaker nature of the low‐k dielectric material can pose significant challenges to downstream electronic‐packaging processes and materials. The purpose of this paper is to focus on the wire bonding of gold wires on a Cu/low‐k pad structure.


The paper presents a numerical model description and simulation procedure.


Numerical methods, particularly finite element method based simulations are a good tool to visualize and understand the reasons for success or failure during a bonding process. It enables one to relate the induced stress to the inherent bulk material's strength and interfacial strength. The results from such simulations clearly indicate the high‐stress locations and the amount of plastic strain that accumulates during the application of compressive force, heat and ultrasonic energy.


These simulations help to understand the device's weaknesses and correlate the failures so as to design the wire bonder equipment with better process control features.



Narasimalu, S. (2008), "Wire bond challenges in low‐k devices", Microelectronics International, Vol. 25 No. 1, pp. 34-40.



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Copyright © 2008, Emerald Group Publishing Limited

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