This paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a WLAN transmitter application in 0.18‐μm deep submicron CMOS technology.
A folded current draining low‐voltage mixer architecture is explored and an extensive simulation carried out utilizing Cadence Spectre‐RF tool in optimizing the linearity, input third‐order intercept point (IIP3), the dynamic range, 1 dB compression point (P−1dB), power dissipation and reduction of switching quad Cgs, input gate‐source capacitance, in enhancing the switching efficiency of the proposed architecture.
A highly linear, high input dynamic range, low voltage folded up‐conversion mixer architecture is realized in a significant comparable performance with respect to conventional reported architecture, indicating −8.87 dBm of OIP3 corresponding to 15.27 dBm IIP3 and 4.37 dBm of P−1dB in 0.18‐μm CMOS technology.
The optimized mixer architecture is stringent to an up‐converter application. To be utilized as a down converter at the receiver end, parameters, namely as noise figure and conversion gain, are of additional importance.
The designed folded mixer architecture is in need of integration to a two‐step up‐conversion transmitter architecture which relaxes the injection pulling effect for a given low voltage headroom, with low power dissipation design.
In this work, an integrated folded architecture with on‐chip process, voltage and temperature compensated biasing circuit is explored and enhanced, raising awareness of adapting improved multiplier blocks in achieving optimal performance in WLAN transceiver architecture.
Ramiah, H. and Zainal Azni Zulkifli, T. (2007), "A 3.5‐GHz, low voltage, current draining folded mixer in 0.18‐
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