TY  - JOUR
AB  - Purpose– In this short communication, transition times of input signals for various stages of a repeater‐chain loaded VLSI interconnects are studied.Design/methodology/approach– SPICE simulations.Findings– It is observed that for a fixed number of repeaters a smaller load will reduce transition time. The effect is not very significant, if the load is moderate.Originality/value– Method can be very useful for short‐circuit power estimation in repeater‐chains.
VL  - 22
IS  - 3
SN  - 1356-5362
DO  - 10.1108/13565360510610530
UR  - https://doi.org/10.1108/13565360510610530
AU  - Chandel Rajeevan
AU  - Sarkar S.
AU  - Agarwal R.P.
PY  - 2005
Y1  - 2005/01/01
TI  - Transition time considerations in repeater‐chains
T2  - Microelectronics International
PB  - Emerald Group Publishing Limited
SP  - 39
EP  - 40
Y2  - 2024/05/10
ER  -