Transition time considerations in repeater‐chains
Rajeevan Chandel
(Department of Electronics & Communication Engineering, National Institute of Technology, Hamirpur HP, India)
S. Sarkar
(Department of Electronics & Computer Engineering, Indian Institute of Technology, Roorkee, Uttaranchal, India)
R.P. Agarwal
(Department of Electronics & Computer Engineering, Indian Institute of Technology, Roorkee, Uttaranchal, India)
179
Abstract
Purpose
In this short communication, transition times of input signals for various stages of a repeater‐chain loaded VLSI interconnects are studied.
Design/methodology/approach
SPICE simulations.
Findings
It is observed that for a fixed number of repeaters a smaller load will reduce transition time. The effect is not very significant, if the load is moderate.
Originality/value
Method can be very useful for short‐circuit power estimation in repeater‐chains.
Keywords
Citation
Chandel, R., Sarkar, S. and Agarwal, R.P. (2005), "Transition time considerations in repeater‐chains", Microelectronics International, Vol. 22 No. 3, pp. 39-40. https://doi.org/10.1108/13565360510610530
Publisher
:Emerald Group Publishing Limited
Copyright © 2005, Emerald Group Publishing Limited