Repeater insertion in global interconnects in VLSI circuits

Abstract

Purpose

Delay and power dissipation are the two major design constraints in very large scale integration (VLSI) circuits. These arise due to millions of active devices and interconnections connecting this gigantic number of devices on the chip. Important technique of repeater insertion in long interconnections to reduce delay in VLSI circuits has been reported during the last two decades. This paper deals with delay, power dissipation and the role of voltage‐scaling in repeaters loaded long interconnects in VLSI circuits for low power environment.

Design/methodology/approach

Trade off between delay and power dissipation in repeaters inserted long interconnects has been reviewed here with a bibliographic survey. SPICE simulations have been used to validate the findings.

Findings

Optimum number of uniform sized CMOS repeaters inserted in long interconnects, lead to delay minimization. Voltage‐scaling is highly effective in reduction of power dissipation in repeaters loaded long interconnects. The new finding given here is that optimum number of repeaters required for delay minimization decreases with voltage‐scaling. This leads to area and further power saving.

Research limitations

The bibliographic survey needs to be revised in future, taking the various other aspects of VLSI interconnects viz. noise, cross talk extra into account.

Originality/value

The paper is of high significance in VLSI design and low‐power high‐speed applications. It is also valuable for new researchers in this emerging field.

Citation

Chandel, R., Sarkar, S. and Agarwal, R.P. (2005), "Repeater insertion in global interconnects in VLSI circuits", Microelectronics International, Vol. 22 No. 1, pp. 43-50. https://doi.org/10.1108/13565360510575549