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2D analysis of functional stress degradations on power VDMOS transistor

B. Beydoun (Laboratoire des Physiques de Matériaux (LPM), Faculté des Sciences, Université Libanaise, Beyrouth, Lebanon)
M. Zoaeter (Laboratoire des Physiques de Matériaux (LPM), Faculté des Sciences, Université Libanaise, Beyrouth, Lebanon)
A. Alaeddine (Laboratoire des Physiques de Matériaux (LPM), Faculté des Sciences, Université Libanaise, Beyrouth, Lebanon)
I. Rachidi (Laboratoire des Physiques de Matériaux (LPM), Faculté des Sciences, Université Libanaise, Beyrouth, Lebanon)
F. Bahsoun (Laboratoire des Physiques de Matériaux (LPM), Faculté des Sciences, Université Libanaise, Beyrouth, Lebanon)
J‐J. Charlot (ENST, Paris, France)
J‐P. Charles (Université de Metz, Metz, France)

Microelectronics International

ISSN: 1356-5362

Publication date: 1 August 2004

Abstract

Modifications of physical and electrical properties of the vertical double‐diffused metal oxide semiconductor (VDMOS) transistor are observed on using the device under some conditions of “functional” stress. This paper presents the characterization and the 2D simulation for the pre‐ and post‐stressed device, to point out the degraded parameters due to the functional stress, and to analyze their effects on the degradation of the VDMOS static and dynamic characteristics.

Keywords

Citation

Beydoun, B., Zoaeter, M., Alaeddine, A., Rachidi, I., Bahsoun, F., Charlot, J. and Charles, J. (2004), "2D analysis of functional stress degradations on power VDMOS transistor", Microelectronics International, Vol. 21 No. 2, pp. 16-22. https://doi.org/10.1108/13565360410531971

Publisher

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Emerald Group Publishing Limited

Copyright © 2004, Emerald Group Publishing Limited