Strategies for improving the reliability of solder joints on power semiconductor devices

Guo‐Quan Lu (Departments of Materials Science and Engineering and Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, USA)
Xingsheng Liu (Departments of Materials Science and Engineering and Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, USA (Currently with Corning Inc., Science and Technology Center, Corning, NY, USA))
Sihua Wen (Department of Biochemistry and Biophysics, University of Pennsylvania, Philadelphia, Pennsylvania, USA)
Jesus Noel Calata (Department of Materials Science and Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, USA)
John G. Bai (Department of Materials Science and Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, USA)

Soldering & Surface Mount Technology

ISSN: 0954-0911

Publication date: 1 August 2004

Abstract

In this paper, some strategies taken to improve the reliability of solder joints on power devices in single device and multi‐chip packages are presented. A strategy for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilization of flexible substrates is discussed with emphasis on triple‐stacked solder joints that resemble the shape of an hourglass. The hourglass shape relocates the highest inelastic strain away from the weaker interface with the chip to the bulk region of the joint, while the underfill provides a load transfer from the joints. Thermal cycling data show significant improvements in reliability when these techniques are used. The design, testing and finite‐element analyses of an interconnection structure, termed the Dimple‐Array Interconnect, for improving the solder joint reliability is also presented.

Keywords

Citation

Lu, G., Liu, X., Wen, S., Noel Calata, J. and Bai, J.G. (2004), "Strategies for improving the reliability of solder joints on power semiconductor devices", Soldering & Surface Mount Technology, Vol. 16 No. 2, pp. 27-40. https://doi.org/10.1108/09540910410537309

Publisher

:

Emerald Group Publishing Limited

Copyright © 2004, Emerald Group Publishing Limited

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