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On integrated circuit chip reduction

Edward T. Lee (L & P Culture and Technology, Inc., San Diego, California, USA)
Eddy T. Lee (L & P Culture and Technology, Inc., San Diego, California, USA)


ISSN: 0368-492X

Article publication date: 1 April 2000



Boolean algebra, Karnaugh map method and Quine‐McClusky algorithm are usually the tools used for minimizing logic functions using gates. However, with the advent of IC chips, the criteria for implementing a low‐cost circuit have been changed from logic gate reduction to IC chip reduction. In this paper, the IC chip reduction problem is systematically analyzed and illustrated by examples. More specifically, the direct mapping method, the IC chip diagram, the IC chip usage table, the reduced IC chip usage table and the reduced IC chip diagram are created and used for IC chip reduction. The reduction process is illustrated step by step with examples. In addition, six substitution rules for reducing the IC chip usage table are also presented. The IC chip reduction problem is both theoretically challenging and practically useful. The results may have useful applications in picture description reduction, picture semantic network reduction as well as in other related areas. It illustrates the effectiveness of a cybernetic approach.



Lee, E.T. and Lee, E.T. (2000), "On integrated circuit chip reduction", Kybernetes, Vol. 29 No. 3, pp. 381-386.




Copyright © 2000, MCB UP Limited

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