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A circuital formulation for direct electrical resistive tomography problems

F. Ferraioli (Dipartimento di Ingegneria dell' Informazione, Seconda Università di Napoli, Aversa, Italy)
A. Formisano (Dipartimento di Ingegneria dell' Informazione, Seconda Università di Napoli, Aversa, Italy)
R. Martone (Dipartimento di Ingegneria dell' Informazione, Seconda Università di Napoli, Aversa, Italy)
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Abstract

Purpose

Electrical resistive tomography (ERT) is a non‐destructive testing technique based upon the reconstruction of the electrical conductivity profile inside a body from measurement made on its boundary. In the literature about the inverse problems the ERT is considered still challenging being both non‐linear, ill‐posed and very limited in resolution. Purpose of the paper is to assess the performances of an approach exploiting the circuital behaviour of a particular class of problems, highlighting its advantages in terms of simplicity and reduction of the computer burden.

Design/methodology/approach

In this paper, an electrical property of a particular class of problems is pointed out; the same property is used to formulate in terms of a circuital model the ERT problem. The proposed methodology consists basically of combining properly simplified data previously evaluated and collected. The overall procedure is presented with reference to an underground structure diagnostics problem.

Findings

The effectiveness of the proposed approach has been evaluated quantitatively by comparing the simplified procedure results with the ones obtained by performing fully 3D FEM analysis.

Originality/value

The consistently low errors obtained state the convenience of the method also taking into account that the reconstruction process consists merely in post‐processing previously collected data.

Keywords

Citation

Ferraioli, F., Formisano, A. and Martone, R. (2005), "A circuital formulation for direct electrical resistive tomography problems", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 24 No. 3, pp. 858-868. https://doi.org/10.1108/03321640510598184

Publisher

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Emerald Group Publishing Limited

Copyright © 2005, Emerald Group Publishing Limited

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